Unit 2

COMPUTERS ORGANIZATION
2ND YEAR COMPUTE SCIENCE
MANAGEMENT ENGINEERING
UNIT 2 – CONTROL UNIT
JOSÉ GARCÍA RODRÍGUEZ
JOSÉ ANTONIO SERRA PÉREZ
Tema 2. La Unidad Central de Proceso
1
Central Process Unit
The processor
Introduction
Buses use
Stages in the Instructions Execution
Control Unit
Control signals identification
Control signals activation
Design of the Control Unit
Introduction
Establishment of the stages
Data path
States Table Method
Sequence Counter Method
Machine abstraction
Conclusions
Tema 2. La Unidad Central de Proceso
2
Introduction
The processor
Way of working of the instructions execution
Control Unit Design
Unidad de
proceso
Dirección
Datos
Unidad de
Memoria
Unidad de
Control
Tema 2. La Unidad Central de Proceso
Lectura
Escritura
3
Chosen Instructions Set
Instructions
Type 1 Format
7
0
OPC
8 bits
Operation
Addition
Subtraction
And
Or
Syntax
ADD r1
SUB r1
ANA r1
ORA r1
Description
A ← A + r1
A ← A − r1
A ← A and r1
A ← A or r1
Tema 2. La Unidad Central de Proceso
Op. Code
30h, 31h, 32h, 33h, 45h
18h, 19h, 1Ah, 1Bh, 46h
20h, 21h, 22h, 23h, 48h
24h, 25h, 26h, 27h, 49h
4
Chosen Intructions Set
Instructions
Type 2 Format
15
8 7
OPC
8 bits
Operation
Syntax
Immediate Addition
Immediate Subtract.
Immediate And
Immediate Or
ADI data
SUI data
ANI data
ORI data
0
Data
8 bits
Description
A ← A + data
A ← A − date
A ← A and date
A ← A or date
Tema 2. La Unidad Central de Proceso
Op. Code
35h
36h
68h
69h
5
Chosen Instructions Set
Instructions
Type 3 Format
23
16 15
OPC
8 bits
8 7
DisplacementL
8 bits
Operation
Syntax
Load
LDA addr
Store
STA addr
Unconditional Jump
Jump if FZ=1
JMP addr
JZ addr
0
displacementH
8 bits
Description
A ← M (addr)
M (addr) ← A
PC ← addr
If FZ = 1 ⇒ PC ← addr
Tema 2. La Unidad Central de Proceso
Op. Code
70h
71h
74h
72h
6
Data path with a single bus
Buses use
8 bits single bus for data
16 bits single bus for address
Temporal registers are needed to free the bus
A
TEMP
HL
Memory
R. B.
ALU
Tema 2. La Unidad Central de Proceso
7
Data path with two buses
Buses use
Two 8 bits buses
Memory communication using HL
Bus link
A
B. R.
ALU
HL
Memoria
Enlace
Tema 2. La Unidad Central de Proceso
8
Data path with 3 buses
Buses use
Three 8 bits buses
Memory communication using HL
Bus link
Enlace
A
B. R.
HL
Memoria
ALU
Tema 2. La Unidad Central de Proceso
9
Instructions Execution Stages
Introduction
Instruction
look up
Flank fired design.
Each stage will go on for
one clock cycle.
Duration for a clock cycle
will depend on the lowest
action’s duration.
A read and a write
operation in the register
bank can not be done in
the same clock cycle.
Decoding
Execution
Operand look
up
Execution
Result Store
Next instruction
preparation
Tema 2. La Unidad Central de Proceso
10
Considerations
Execution
Stages
Basic functions of MaNoTas:
Assumptions:
Access to Registers Bank
Access to Memory
ALU Operations
The time for these functions is equal to a clock cycle.
Others elements’ cost is zero.
Actions bound to a stage are done in parallel.
Actions bound to successive stages are done
serially.
Tema 2. La Unidad Central de Proceso
11
Stages
Execution
Stages
Stage 1
Stage 2
IR←M[PC]
PC←PC + 1
PC ←Pc+1
Decoding
PC ←Pc+1
ADD,SUB,ANA,ORA
Stage 3
ADI,SUI,ANI,ORI
TEMP←r1
JZ
LDA,STA,JMP
TEMP←M[PC]
PC ←PC+1
L←M[PC]
PC ←PC+1
(Z)=1
Stage 4
A←A op TEMP
Stage 5
si
A←A op TEMP
LDA
A←M(HL)
L←M[PC]
PC ←PC+1
H←M[PC]
PC ←PC+1
STA
JMP
M(HL)←A
PC←HL+1
H←M[PC]
PC ←PC+1
Stage 6
PC←HL+1
Tema 2. La Unidad Central de Proceso
12
Stages Establishment (1)
Execution
Stages
Stage1: Instruction look up
IR ← M[PC]
PC ← PC + 1
Stage 2. Decoding
This two stages are common to all instructions
Tema 2. La Unidad Central de Proceso
13
Stages Establishment (2)
Execution
Stages
Stage 3: Operands obtaining and code
evaluation for the Z condition.
Case I. Arithmetic-Logic Instructions
Direct to register addressing mode
TEMP ← r1
Immediate addressing mode
TEMP ← M[PC]
PC ← PC +1
(TEMP ← data)
Case II. Reference to memory instructions and unconditional
jump
L ← M[PC]
PC ← PC +1
(L ← AddrL)
Case III. Conditional jump instruction
Z?
Tema 2. La Unidad Central de Proceso
14
Stages Establishment (3)
Execution
Stages
Stage 4: Operands obtaining, execution
and end of Arithmetic-Logic instructions.
Case I. Arithmetic-Logic Instructions
A ← A op TEMP
Case II. Reference to memory instructions and unconditional
jump
H ← M[PC]
PC ← PC +1
(H ← AddrH)
Case III. Conditional jump instruction
L ← M[PC]
PC ← PC +1
(L ← AddrL)
Tema 2. La Unidad Central de Proceso
15
Stages Establishment (4)
Execution
Stages
Stage 5: End of access to memory
instructions and unconditional jump and
operand obtaining.
Case I. Reference to memory instructions
Load instruction
Store instruction
M[HL] ← A
Case II. Unconditional jump instruction
A ← M[HL]
PC ← HL +1
Case III. Conditional jump instruction
H ← M[PC]
PC ← PC +1
(H ← AddrH)
Tema 2. La Unidad Central de Proceso
16
Stages Establishment (5)
Execution
Stages
Stage 6: End of unconditional jump
instruction.
PC ← HL +1
Tema 2. La Unidad Central de Proceso
17
Final stages diagram
Execution
Stages
RI←M[PC]
PC←PC + 1
Stage 1
Stage 2
PC ←Pc+1
JZ if Z=0
Decoding
Z evaluation
PC ←Pc+1
ADD,SUB,ANA,ORA
Stage 3
ADI,SUI,ANI,ORI
TEMP←r1
JZ if Z=1
LDA,STA,JMP
TEMP←M[PC]
PC←PC+1
L←M[PC]
PC←PC+1
L←M[PC]
PC←PC+1
A←A op TEMP
H←M[PC]
PC←PC+1
H←M[PC]
PC←PC+1
Stage 4
A←A op TEMP
Stage 5
LDA
A←M(HL)
Tema 2. La Unidad Central de Proceso
STA
JMP
M(HL)←A
PC←HL+1
PC←HL+1
18
Data path
Execution
Stages
+1
±1
PC
0
1 MX
2
SP
IR
direction
MEMORY
HL
data
A
Registers
Bank
M
X
TEMP
Modification
ALU
S. R.
Tema 2. La Unidad Central de Proceso
19
Identification of the control signals(1)
Control
Unit
Output control signals for the registers bank
Signal
SELreg1
Description
REGISTERS BANK CONTROL
This two signals select the register which should be accessed: B, C, D or E.
SELreg0
Lreg
If it is set (value 1), allows the data that is in the bus to be stored in the
selected register.
Sreg
If it is set (value 1), allows the data that is in the selected register to appears
in the bus.
Tema 2. La Unidad Central de Proceso
20
Identification of the control signals(2)
Control
Unit
Output control signals for the memory and the ALU
Signal
Description
MEMORY CONTROL
Lmem
Memory load signal. If its value is 1, the data stored in the address pointed
by the address bus is placed in the data bus.
Smem
Memory store signal. If its value is 1, the data present in the data bus is
stored in the address pointed by the address bus.
SAddr2
These signals contol the multiplexor that selects the data to be placed in the
address bus for access the memory. Depending of its value, the memory
address that will be accessed would be set by the PC, SP or HL register.
SAddr1
ARITHMETIC LOGIC UNIT CONTROL
ALU2
ALU1
These three control signals set the operation that will perform the ALU:
addition, subtraction, and, or, xor, increment and decrement.
ALU0
Salu
If this signal is set, the ALU result will be placed in the data bus.
Tema 2. La Unidad Central de Proceso
21
Identification of the control signals(3)
Control
Unit
Output control signals for the status register
Signal
Description
STATUS REGISTER CONTROL
LF
If the signal is set, loads the data in the status register. The data can come
from the ALU or from the accumulator register.
SF
If the signal is set, stores in the data bus the data stored in the status
register.
SelO
It controls the multiplexor that selects the data to write in the status register
as the Overflow flag: bit 2 from the accumulator register or the overflow flag
coming from the ALU.
SelC
It controls the multiplexor that selects the data to write in the status register
as the Carry flag: bit 1 from the accumulator register or the carry flag coming
from the ALU.
SelZ
It controls the multiplexor that selects the data to write in the status register
as the Zero flag: bit 0 from the accumulator register or the zero flag coming
from the ALU.
Tema 2. La Unidad Central de Proceso
22
Identification of the control signals(4)
Control
Unit
Output control signals for the registers and input
control signals.
Signal
Description
REGISTERS CONTROL
Lir
If set, the data present in the data bus is stored in the instruction register.
Lpc
If set, the data present in the input of the program counter is loaded.
LspL
If set, the data present in the data bus is loaded in the low order byte of the SP register.
LspH
If set, the data present in the data bus is loaded in the high order byte of the SP register.
Isp
If set, the content of the SP register is increased by 1.
Dsp
If set, the content of the SP register is decreased by 1.
LaddrL
If set, the data present in the data bus is loaded in the low order byte of the HL register.
LaddrH
If set, the data present in the data bus is loaded in the high order byte of the HL register.
Lac
If set, the data present in the data bus is loaded in the accumulator register.
Sac
If set, the data in the accumulator register is placed in the data bus.
Ltemp
If set, the data present in the data bus is stored in the temporal register.
CONTROL INPUTS
Z
The Z flag generated by the ALU.
OPC
Operation code, is the content of the instruction register.
Tema 2. La Unidad Central de Proceso
23
Identification of the control signals(5)
Control
Unit
Control signals for the multiplexors, the register bank
and the ALU.
SAddr2
0
0
1
1
SELreg1 SELreg0 Register
0
0
B
0
1
C
1
0
D
1
1
E
SelO
0
1
ALU2
0
0
0
0
1
1
1
1
ALU1
0
0
1
1
0
0
1
1
ALU0
0
1
0
1
0
1
0
1
Operation
Addition
Subtraction
And
Or
Xor
Increment
Decrement
Unused
Action
O←ALUO
O←A2
SelC
0
1
Action
C←ALUC
C←A1
SelZ
0
1
Tema 2. La Unidad Central de Proceso
SAddr1
0
1
0
1
Address
PC
SP
HL
Unused
Action
Z←ALUZ
Z←A0
24
Data and control path
Control
Unit
SelZ
SF
CONTROL
LF
UNIT
SELreg1, 0
Sreg
Lreg
Lir LspH LspL Dsp Isp LAddrH Lpc
ALU2,1,0
Salu
LTemp
Lac
Sac
Lmem
Smem
LAddrL SAddr2,1
+1
±1
PC
0
1 MX
2
SP
IR
HL
Address
MEMORY
data
A
TEMP
Registers
Bank
M
X
ALU
S.R. .
Tema 2. La Unidad Central de Proceso
25
Control signals activation
These instructions will not be considered: ADD A, SUB A, ANA A y ORA A
Control
Unit
Stages
Operation
Signals activation
RI ← M[PC]
SAddr2, SAddr1(=00), Lmem, Lir,
PC ← PC + 1
Lpc
STAGE 1
STAGE 2
Decoding
evaluation of Z
and
STAGE 3
ADD, SUB, ANA, ORA
TEMP ← r1
SELreg1,SELreg0 (=r1), Sreg, Ltemp
ADI, SUI, ANI, ORI
TEMP ← M[PC]
Ltemp, Lmem, SAddr2, SAddr1(=00)
PC ← PC + 1
Lpc
L ← M[PC]
LAddrL, Lmem, SAddr2, SAddr1(=00)
PC ← PC + 1
Lpc
Arithmetic-Logic
A ← A op TEMP
ALU2, ALU1, ALU0 (=operation), Salu, Lac
Transfer and jump
H ← M[PC]
LAddrH, Lmem, SAddr2, SAddr1(=00)
PC ← PC + 1
Lpc
LDA
A ← M(HL)
SAddr2,SAddr1 (=10), Lmem,Lac
STA
M(HL) ← A
SAddr2,SAddr1 (=10), Smem, Sac
LDA, STA, JMP, JZ
STAGE 4
STAGE 5
JMP, JZ
← HL
+ 1 CentralSAddr2,SAddr1
TemaPC
2. La
Unidad
de Proceso (=10), Lpc
26
Stage 1 of the execution of LDA
Control
Unit
SelZ
SF
LF
CONTROL
UNIT
SELreg1, 0
Sreg
Lreg
Lir LspH LspL Dsp Isp LAddrH Lpc
ALU2,1,0
Salu
LTemp
Lac
Sac
Lmem
Smem
LAddrL SAddr2,1
+1
±1
PC
0
1 MX
2
SP
IR
HL
address
MEMORY
data
A
TEMP
Register
Bank
M
X
ALU
S. R.
Tema 2. La Unidad Central de Proceso
27
Stage 2 of the execution of LDA
Control
Unit
SelZ
CONTROL
SF
LF
UNIT
SELreg1, 0
Sreg
Lreg
Lir LspH LspL Dsp Isp LAddrH Lpc
LAddrL
ALU2,1,0
Salu
LTemp
Lac
Sac
Lmem
Smem
SAddr2,1
+1
±1
PC
0
1 MX
2
SP
IR
HL
address
MEMORY
data
A
Register
Bank
M
X
TEMP
ALU
S. R.
Tema 2. La Unidad Central de Proceso
28
Stage 3 of the execution of LDA
Control
Unit
SelZ
CONTROL
SF
LF
UNIT
SELreg1, 0
Sreg
Lreg
Lir LspH LspL Dsp Isp LAddrH Lpc LAddrL
ALU2,1,0
Salu
LTemp
Lac
Sac
Lmem
Smem
SAddr2,1
+1
±1
PC
0
1 MX
2
SP
IR
HL
address
MEMORY
data
A
Register
Bank
M
X
TEMP
ALU
S. R.
Tema 2. La Unidad Central de Proceso
29
Stage 4 of the execution of LDA
Control
Unit
SelZ
SF
LF
CONTROL
UNIT
SELreg1, 0
Sreg
Lreg
Lir LspH LspL Dsp Isp LAddrH Lpc
ALU2,1,0
Salu
LTemp
Lac
Sac
Lmem
Smem
LAddrL SAddr2,1
+1
±1
PC
0
1 MX
2
SP
IR
HL
address
MEMORY
data
A
TEMP
Register
Bank
M
X
ALU
S. R.
Tema 2. La Unidad Central de Proceso
30
Stage 5 of the execution of LDA
Control
Unit
SelZ
SF
LF
CONTROL
UNIT
SELreg1, 0
Sreg
Lreg
Lir LspH LspL Dsp Isp LAddrH Lpc
ALU2,1,0
Salu
LTemp
Lac
Sac
Lmem
Smem
LAddrL SAddr2,1
+1
±1
PC
0
1 MX
2
SP
IR
HL
address
MEMORY
data
A
TEMP
Register
Bank
M
X
ALU
S. R.
Tema 2. La Unidad Central de Proceso
31
LDA addr
Control
Unit
SAddr2-1
00
ZZ
00
00
02
L
Lir
LPc
LAddrL
LAddrH
LAc
Instruction
look up Stage
Decoding
Execution
Stage
Tema 2. La Unidad Central de Proceso
32
Control Unit Design
Control
Unit
Design
Wired Control.
Microprogrammed Control.
Implemented with Hardware, therefore very fast.
It is not flexible: a posterior modification implies to change the
whole circuit.
Programmed representation for the control.
Slower, as the control memory must be accessed.
Flexible, it allows posterior modifications with out change the
whole circuit.
Two methods to design a wired control unit
State table method
Sequence counter method
Tema 2. La Unidad Central de Proceso
33
State table method
Wired
Control
Unit
Based on a finite state machine.
A finite state machine consists:
An internal memory that holds the state and
Two combinatories functions:
The next state function
The output function
Each state corresponds to a clock cycle and contains the
operations to be done on that cycle.
The next state function is a combinatory function that using its
inputs and the current state determines the next state.
The output function produced the set of control signals from its
inputs and the current state.
Tema 2. La Unidad Central de Proceso
34
States graph
0/S0
State
Table
Method
C.Op.=XXXX
Z=X
30h,18h, 20h, 24, X
C.Op.=72h
Z=0
1/S1
70h, 71h, 74h ,X
72h, 1
35h, 36h, 68h, 69h,X
8/S8
3/S3
2/S2
30h,X
36h,X
35h,X
18h,X
69h,X
68h,X
20h,X
XX,X
24h,X
XX,X
4/S4
5/S5
7/S7
6/S6
9/S9
72h,74h,X
XX,X
XX,X
70h,X
XX,X
71h,X
XX,X
11/S11
10/S10
Tema 2. La Unidad Central de Proceso
XX,X
12/S12
XX,X
35
Output function
State
Table
Method
As arithmetic-logic instructions, we only consider: Add B, SUB B, ANA B y ORA B
Output function
Control signals
Lir
SAddr2,1
Lmem
Smem
Lpc
LspL
LspH
Isp
Dsp
LaddrL
LaddrH
SELreg1,0
Lreg
Sreg
Lac
Sac
Ltemp
ALU2,1,0
Salu
Sel0
SelC
SelZ
LF
SF
States
0
1
2
3
4
1
0
0
0
0
00
XX XX
00
XX
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XX XX
00
XX XX
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
XXX XXX XXX XXX 000
0
0
0
0
1
X
X
X
X
0
X
X
X
X
0
X
X
X
X
0
0
0
0
0
1
0
0
0
0
0
5
6
0
XX
0
0
0
0
0
0
0
0
0
XX
0
0
1
0
0
001
1
0
0
0
1
0
0
XX
0
0
0
0
0
0
0
0
0
XX
0
0
1
0
0
010
1
0
0
0
1
0
Tema 2. La Unidad Central de Proceso
7
8
9
10
11
12
0
0
0
0
0
0
XX
00
00
10
10
10
0
1
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
XX XX XX XX XX XX
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
011 XXX XXX XXX XXX XXX
1
0
0
0
0
0
0
X
X
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
1
0
0
0
0
0
0
0
0
0
0
0
36
Next state function
State
Table
Method
INSTRUCTION
72h,0 (JZ)
30h,18h,20h,24h,X (ADD,SUB,ANA,ORA)
35h,36h,68h,69h,X (ADI,SUI,ANI,ORI)
70h,71h,74h,X (LDA,STA,JMP);72h,1 (JZ)
30h,X ( ADD)
18h,X (SUB)
20h,X (ANA)
24h,X (ORA)
35h,X (ADI)
36h,X (SUI)
68h,X (ANI)
69h,X (ORI)
70h,X (LDA)
71h,X (STA)
72h,74h , X (JMP, JZ)
E3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
E2
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
Tema 2. La Unidad Central de Proceso
E1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
E0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
1
1
0
1
0
PE3 PE2 PE1 PE0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
37
Control Unit Implementation
State
Table
Method
Lri
SDir2, SDir1
Lmem
Emem
Control unit built as a
finite state machine.
The combinatory
circuit could be
implemented using a
ROM or a PLA.
Lpc
LspH, LspL
Isp, Dsp
Lógica de
Control
Salidas
LdirH, LdirL
SELreg1,SELreg0
Lreg,Sreg
Lac, Sac
Ltemp
ALU1,Alu1,ALu0
Salu
SelO,SelC,SelZ
LF,SF
PE3
PE2
PE1
PE0
Entradas
C7 C6 C5 C4 C3 C2 C1 C0 Z
Código de Operación
y Flag Z
Tema 2. La Unidad Central de Proceso
E3 E2 E1 E0
Registro
de estado
38
Control Unit Implementation
State
Table
Method
•
•
•
•
•
A PLA (programmable logic array) is a general purpose
programmable logic element to implement any
combinatory function.
A PLA is form by:
A set of inputs and outputs
A set of AND gates that form a set of product terms.
A set of OR gates, each of them form a logic sum of any
product term.
A set of negators for the inputs.
Two arrays of modifiable connections (AND & OR)
Tema 2. La Unidad Central de Proceso
39
Control Unit Implementation
S0
S1
24h
S1
72h,1
S12
En0
...
En8
......
......
......
......
......
......
......
......
......
......
......
......
Ea0
Ea1
Ea2
32
13
5
4
3
2
Ea3
1
State
Table
Method
S1
S1 S1
30h 18h 20h
1
2
.......
.
.......
.
Array OR
Tema 2. La Unidad Central de Proceso
Lir, Lmem,Lpc
Saddr2,1=00
SELreg1,0=00
Sreg,Ltemp
...
...
Output
1
Ef0
1
1
Ef1
Ef2
1
Ef3
40
Control Unit Implementation
State
Table
Method
The size of a PLA is equal to the addition of the size of the
AND gates array and the size of the OR gates array.
For MaNoTaS = (13xnumber of different product terms) +
(32xnumber of sum terms).
A PLA is more efficient than a ROM because it doesn’t
stores a full truth table, instead it does a minimal addition
of products.
Programming a PLA is harder than programming a ROM.
Tema 2. La Unidad Central de Proceso
41
Sequence counter method
Wired
Control
Unit
It is based on a module
K counter which outputs
are connected to a
decoder generating a
individual signal on
each stage.
The counter pass throught
each state on each cycle
The decoder generates K
pulsed signals {Φj} which
are the stage signals.
All the stages have the same
duration (equal to a clock
cycle)
reloj
Contador
Módulo K
Puesta a cero
DECODIFICADOR
Φ1
Φk
Φ2
fases
Φ1
Φ2
Φ3
ΦK
Tema 2. La Unidad Central de Proceso
42
Control Unit Implementation
Stages
Counter
Method
Each control signal is obtained as:
ci = ∑ Φ j ∑ Im Sl
j
m
Puesta a cero
Contador de fases
Φ0
ADD
SUB
ANA
ORA
Decodificado
r de
instruccione
s
ADI
SUI
ANI
ORI
LDA
Φ1
Φ2
Φ3
Φ4
Lri
SDir2, SDir1
Lmem
Emem
Lógica de control
combinacional
STA
JMP
JZ
Lpc
LspH, LspL
Isp, Dsp
Salidas
LdirH, LdirL
SELreg1,SELreg0
Lreg,Sreg
Lac, Sac
Ltemp
ALU1,Alu1,ALu0
Salu
SelO,SelC,SelZ
LF,SF
Z
IR[8-0]
Tema 2. La Unidad Central de Proceso
43
Logic function examples
Stages
Counter
Method
Output logic functions for some control signals.
Signal
Output logic function
(
)
Zero
Φ14 ⋅ JZ ⋅ Z + Φ4 ⋅ (add + adi) + Φ5 ⋅ (sub + sui) + Φ6 ⋅ (ana + ani) + Φ7 ⋅
+ Φ10 ⋅ lda + Φ11 ⋅ sta + Φ12 ⋅ ( jmp + JZ·Z )
Lpc
Φ0 + Φ 2 ⋅ (adi + sui + ani + ori + lda + sta + jmp + jz ⋅ Z )
ALU1
Φ 3 ⋅  ana + ani + ora + ori 
ALU0
Φ 3 ⋅ (sub + sui + ora + ori )
Φ 4 ⋅ sta
Smem
Tema 2. La Unidad Central de Proceso
44
Machine abstraction
MaNoTas
CONTROL
BUS de control
BUS de
direcciones
RUTA DE
DATOS
MEMORIA
BUS de datos
ROCESADOR
Tema 2. La Unidad Central de Proceso
45
Conclusions
Conclusions
The data path structure has influence on the establishment of
the stages.
The structure of the instruction set has influence on the data
path.
The wired Control Unit is very efficient as the control signals
are activated directly by the hardware.
It is suitable when the instructions set is not much complex.
However it is not flexible on posterior modifications.
The different design methods for the control unit are all
equivalents, differing only by its facility to obtain the logic
functions for the control signals.
Tema 2. La Unidad Central de Proceso
46