MM54HC85/MM74HC85 4-Bit Magnitude Comparator

MM54HC85/MM74HC85
4-Bit Magnitude Comparator
General Description
The comparator’s outputs can drive 10 low power Schottky
TTL (LS-TTL) equivalent loads, and is functionally, and pin
equivalent to the 54LS85/74LS85. All inputs are protected
from damage due to static discharge by diodes to VCC and
ground.
The MM54HC85/MM74HC85 is a 4-bit magnitude comparator that utilizes advanced silicon-gate CMOS technology. It
is designed for high speed comparison of two four bit words.
This circuit has eight comparison inputs, 4 for each word;
three cascade inputs (AkB, AlB, A e B); and three decision outputs (AkB, AlB, A e B). The result of a comparison
is indicated by a high level on one of the decision outputs.
Thus it may be determined whether one word is ‘‘greater
than,’’ ‘‘less than,’’ or ‘‘equal to’’ the other word. By connecting the outputs of the least significant stage to the cascade inputs of the next stage, words of greater than four bits
can be compared. In addition the least significant stage
must have a high level applied to the A e B input, and a low
level to the A kB, and AlB inputs.
Features
Y
Y
Y
Y
Y
Typical propagation delay: 27 ns
Wide operating voltage range: 2 – 6V
Low input current: 1 mA maximum
Low quiescent current: 80 mA maximum (74HC Series)
Output drive capability: 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL/F/5205 – 1
Order Number MM54HC85 or MM74HC85
Truth Table
Comparing
Inputs
Cascading
Inputs
Outputs
A3, B3
A2, B2
A1, B1
A0, B0
AlB
AkB
AeB
AlB
AkB
AeB
A3 l B3
A3 k B3
A3 e B3
A3 e B3
A3 e B3
A3 e B3
A3 e B3
A3 e B3
A3 e B3
A3 e B3
A3 e B3
A3 e B3
A3 e B3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
H
L
X
X
X
X
X
X
X
X
L
H
X
H
L
X
X
X
X
X
X
X
X
L
L
H
L
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
A2 l B2
A2 k B2
A2 e B2
A2 e B2
A2 e B2
A2 e B2
A2 e B2
A2 e B2
A2 e B2
A2 e B2
A2 e B2
C1995 National Semiconductor Corporation
A1 l B1
A1 k B1
A1 e B1
A1 e B1
A1 e B1
A1 e B1
A1 e B1
A1 e B1
A1 e B1
TL/F/5205
A0 l B0
A0 k B0
A0 e B0
A0 e B0
A0 e B0
A0 e B0
A0 e B0
RRD-B30M115/Printed in U. S. A.
MM54HC85/MM74HC85 4-Bit Magnitude Comparator
November 1995
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
b 0.5 to a 7.0V
Supply Voltage (VCC)
b 1.5 to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5 to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 25 mA
DC Output Current, per pin (IOUT)
g 50 mA
DC VCC or GND Current, per pin (ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temp. (TL) (Soldering 10 seconds)
260§ C
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
0
VCC
Units
V
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
VCC e 2.0V
(tr, tf)
VCC e 4.5V
VCC e 6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
74HC
TA eb40 to 85§ C
Typ
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
8.0
80
160
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Symbol
Parameter
Typ
Limit
Units
tPHL, tPLH
Maximum Propagation Delay Data Input to AkB or AlB
Conditions
20
36
ns
tPHL, tPLH
Maximum Propagation Delay A e B Input to A e B Output
12
20
ns
tPHL, tPLH
Maximum Propagation Delay Cascade Input to Output
13
26
ns
tPHL, tPLH
Maximum Propagation Delay Data Input to A e B
20
30
ns
AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
tPHL, tPLH
Maximum Propagation
Delay Data Input to
Output
2.0V
4.5V
6.0V
100
21
18
210
42
36
265
53
45
313
63
53
ns
ns
ns
tPHL, tPLH
Maximum Propagation Delay
Data Input to A e B Output
2.0V
4.5V
6.0V
88
18
15
175
35
30
221
44
37
261
52
44
ns
ns
ns
tPHL, tPLH
Maximum Propagation Delay
A e B Input to A e B Output
2.0V
4.5V
6.0V
63
13
11
125
25
21
158
32
27
186
37
32
ns
ns
ns
tPHL, tPLH
Maximum Propagation
Delay Cascade Input
to Output (except A e B)
2.0V
4.5V
6.0V
70
16
13
155
31
26
195
39
33
231
46
39
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
25
7
6
75
15
13
95
19
16
110
22
19
ns
ns
ns
CIN
Maximum Input Capacitance
5
10
10
10
pF
CPD
Power Dissipation Capacitance
(Note 5)
80
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption,
IS e CPD VCC f a ICC.
Typical Application
Cascading Comparators
TL/F/5205 – 4
3
TL/F/5205 – 3
Logic Diagram
4
5
MM54HC85/MM74HC85 4-Bit Magnitude Comparator
Physical Dimensions inches (millimeters)
Order Number MM54HC85J or MM74HC85J
NS Package J16A
Order Number MM74HC85N
NS Package N16E
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