CORTEX M4 SET DE INSTRUCCIONES BÁSICO ACCESO DE MEMORIA Mnemonic Operands Description LDR {H,SH,B,SB} LDR {H,SH,B,SB} STR {H,B} STR {H,B} PUSH {Rt1,Rt2,….} POP {Rt1,Rt2,….} ADR MOV, MOVS Rd, [Rn] Rd, [Rn,#offset] Rt, [Rn] Rt, [Rn,#offset] reglist reglist Rd, label Rd, <Op2> Load Register with data Load Register with data Store Register data Store Register data Push registers onto stack Pop registers from stack Set Rd equal to the address at label Set Rd equal to Op2 MOV MVN, MVNS Rd, #imm16 Rd, <Op2> Set Rd equal to imm16 Set Rd equal to -Op2 LDR {H,SH,B,SB} Rd, [Rn],#offset Load Register with data and increment LDR {H,SH,B,SB} Rd, [Rn,#offset]! Load Register with data and increment ARITMÉTICAS Y LÓGICAS Mnemonic Operands Flags Rd = [Rn] Rd = [Rn+off] [Rn] = Rt [Rn+off] = Rt Rd = <label> Rd = Operand2 Rd[15:0] = imm16, Rd[31:16] = 0, imm16 range 0-65535 Rd = 0xFFFFFFFF EOR Operand2 Rd = [Rn] Rn = Rn + off Rn = Rn + off Rd = [Rn] Description N,Z,C - Flags ADD, ADDS ADD, ADDS SUB, SUBS SUB, SUBS RSB, RSBS RSB, RSBS CMP CMN MUL, MULS MLA MLS UDIV SDIV {Rd,} Rn,<Op2> {Rd,} Rn,#imm12 {Rd,} Rn,<Op2> {Rd,} Rn,#imm12 {Rd,} Rn,<Op2> {Rd,} Rn,#imm12 Rn, <Op2> Rn, <Op2> {Rd,} Rn,Rm Rd, Rn,Rm, Ra Rd, Rn,Rm, Ra {Rd,} Rn,Rm {Rd,} Rn,Rm Add Add Subtract Subtract Reverse Subtract Reverse Subtract Compare Compare Negative Multiply, 32-bit result Multiply with Accumulate, 32-bit result Multiply and Subtract, 32-bit result Unsigned Divide Signed Divide Rd = Rn + Operand2 Rd = Rn + imm12, imm12 range 0-4095 Rd = Rn – Operand2 Rd = Rn - imm12, imm12 range 0-4095 Rd = Operand2 – Rn Rd = imm12 – Rn Update PSR flags on Rn – Operand2 Update PSR flags on Rn + Operand2 Rd = Rn * Rm Rd = Ra + (Rn * Rm) Rd = Ra – (Rn * Rm) Rd = Rn / Rm Rd = Rn / Rm AND, ANDS ORR, ORRS ORN, ORNS EOR, EORS BIC, BICS {Rd,} Rn,<Op2> {Rd,} Rn,<Op2> {Rd,} Rn,<Op2> {Rd,} Rn,<Op2> {Rd,} Rn,<Op2> Logical AND Logical OR Logical OR NOT Exclusive OR Bit Clear LSL, LSLS Rd, Rm,Rs Logical Shift Left (unsigned) LSL, LSLS Rd, Rm,#n Logical Shift Left (unsigned) LSR, LSRS Rd, Rm,Rs Logical Shift Right (unsigned) LSR, LSRS Rd, Rm,#n Logical Shift Right (unsigned) ASR, ASRS Rd, Rm,Rs Arithmetic Shift Right (signed) ASR, ASRS Rd, Rm,#n Arithmetic Shift Right (signed) ROR, RORS Rd, Rm,Rs Rotate Right ROR, RORS Rd, Rm,#n Rotate Right RRX, RRXS Rd, Rm Rotate Right with Extend Rd = Rn & Operand2 Rd = Rn | Operand2 Rd = Rn | (~ Operand2) Rd = Rn ^ Operand2 Rd = Rn & (~ Operand2) Rd = Rm << Rs (Same as MOV{S} Rd, Rm, LSL Rs) Rd = Rm >> n (Same as MOV{S} Rd, Rm, LSL n) Rd = Rm << Rs (Same as MOV{S} Rd, Rm, LSR Rs) Rd = Rm >> n (Same as MOV{S} Rd, Rm, LSR n) Rd = Rm >> Rs (Same as MOV{S} Rd, Rm, ASR Rs) Rd = Rm >> n (Same as MOV{S} Rd, Rm, ASR n) Rd = Rm >> Rs (Same as MOV{S} Rd, Rm, ROR Rs) Rd = Rm >> #n (Same as MOV{S} Rd, Rm, ROR n) Rd = RRX(Rm) (Same as MOV{S} Rd, Rm, RRX) ZAS2017-1 N,Z,C N,Z,C,V N,Z,C,V N,Z,C,V N,Z,C,V N,Z,C,V N,Z,C,V N,Z,C,V N,Z N,Z N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C N,Z,C INSTRUCCIONES ESPECIALES Mnemonic Operands CPSID CPSIE CONTROL DE FLUJO Mnemonic Description Operands label Rm Branch to label Branch indirect to location specified by Rm BL label Branch to subroutine at label BLX label o Rm Branch to subroutine indirect specified by Rm o label Operands - Description B BX Mnemonic Flags Change Processor State, Disable Interrupts Change Processor State, Enable Interrupts i i Flags PC = label. label is this instruction ±32MB PC = Rm LR = address of next instruction, PC = label. label is this instruction ±32MB. LR = address of next instruction, PC = Rm[31:1]. O PC = label Meaning BEQ BNE BCS BHS BCC BLO BMI BPL BVS BVC BHI BLS BGE BLT BGT BLE label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm label o Rm {} Rd Encierre operandos opcionales Especifica el registro de destino . Si se omite Rd, el registro de destino es Rn Especifica el registro que contiene el primer operando . Especifica cualquier registro Es un segundo operando flexibles Cualquier valor de 0 a 31 Cualquier valor de -255 a 4095 Cualquier dirección dentro de la memoria ROM Cualquier valor de 0 a 4095 Cualquier valor de 0 a 65535 Dato de 16 bits sin signo Dato de 16 bits con signo Dato de 8 bits sin signo Dato de 8 bits con signo Rn Rt Op2 #n #offset label #imm12 #1mm16 H SH B SB ZAS2017-1 Equal Not equal Higher or same, unsigned Higher or same, unsigned Lower, unsigned Lower, unsigned Negative Positive or zero Overflow No overflow Higher, unsigned Lower or same, unsigned Greater than or equal, signed Less than, signed Greater than, signed Less than or equal, signed Condition Flags Z=1 Z=0 C=1 C=1 C=0 C=0 N=1 N=0 V=1 V=0 C = 1 and Z = 0 C = 0 or Z = 1 N=V N != V Z = 0 and N = V Z = 1 and N != V -