Lenovo IdeaPad 100-15IBD CG410 CG510 NM-A681 Rev0.2

A
B
C
D
E
1
1
LCFC Confidential
CG510 M/B Schematics Document
2
2
Intel Broadwell U-Processor with DDRIIIL + NV920
2015-05-09
REV:0.2
3
3
4
4
Title
LC Future Center Secret Data
Security Classification
Issued Date
2015/02/27
Deciphered Date
Cover Page
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
Custom
Date:
A
B
C
D
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
E
1
of
59
A
B
C
D
LCFC confidential
NV (N16V-GM)
GB2B-64 Package
PCI-Express
4x Gen2
PCIe Port5
Page 18~28
DDR3L-SO-DIMM X1
Memory BUS (CHA)
Page 14,15
1.35V DDR3L 1600 MT/s
VRAM 256/128*16
DDR3L*4 2GB/1GB
1
E
File Name : CG510
1
UP TO 4G
Memory BUS (CHB)
Page 19~28
Memory down 256/128*16
DDR3L*8 4G/2G
1.35V DDR3L 1600 MT/s
HDMI
HDMI Conn.
USB Left
Page 34
USB 3.0 1x
Intel MCP
eDP x2 Lane
eDP Conn
USB 2.0 2x
USB 2.0 Port2
USB2.0 1x
Int. Camera
USB2.0 Port5
Int. MIC Conn.
2
USB2.0 1x
Page 33
SATA HDD
Cardreader Realtek
RTS5170 USB2.0 Port3
SATA Gen3
SATA ODD
BGA-1168
40mm*24mm
SATA Gen1
USB 2.0 1x
PCIe 1x
SATA Port1
NGFF Card
WLAN&BT
PCIe Port4
USB2.0 Port6
Page 40
LAN Realtek
Page 38
PCIe 1x
RTL8106EUL (10M/100M)
3
Page 37
SD/MMC Conn.
SATA Port0
Page 42
RJ45 Conn.
Page 41
Haswell U 15W /
Broadwell U 15W
2
Page 42
USB 3.0 Port1
USB 2.0 Port1
SPI BUS
PCIe Port3
SPI ROM
8MB
3
Page 07
HD Audio
Page 3~13
Codec
Conexant CX11802
Page 43
SPK Conn.
Page 43
EC
ITE IT8586E-LQFP
Page 44
Mic
HP&Mic Combo Conn.
Sub-board ( for 15")
Page 44
Touch Pad
4
Page 45
Int.KBD
Page 45
Thermal Sensor
NCT7718W
ODD Board
4
Page 39
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Block Diagram
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
C
D
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
E
2
of
59
A
B
Voltage Rails ( O --> Means ON
C
D
E
, X --> Means OFF )
+5VS
+VALW
+V
+VS
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+3VS
Power Plane
+1.35VS
+1.05VS
+3VALW
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
Full ON
+1.5VS
1
SIGNAL
STATE
Clock
1
+0.675VS
+3VALW_PCH
B+
CPU_CORE
+1.35V
+5VALW
+VGA_CORE
State
+3VGS
+1.8VGS
+1.35VGS
USB Port Table
+0.95VGS
BOM Structure Table
USB 2.0
XHCI
S0
O
S3
O
O
O
O
O
O
O
O
X
2
0
USB Port (Right Side)
1
USB Port1 (Left Side)
1
2
USB Port2 (Left Side)
2
Cardreader
3
3
S3
Battery only
O
O
S5 S4/AC Only
O
O
O
O
O
X
X
X
USB 3.0
XHCI
4
TOUCH PANEL
5
Camera
6
NGFF(WLAN)
USB Port1 (Left Side)
4
7
S5 S4
Battery only
O
S5 S4
AC & Battery
don't exist
X
X
X
X
X
X
X
X
X
PCIE PORT LIST
SMBUS Control Table
Port
3
SOURCE
EC_SMB_CK1
VGA
EC_SMB_DA1
IT8586E
+3VALW
X
EC_SMB_CK2
IT8586E
V
EC_SMB_DA2
+3VS
+3VGS
BATT
V
X
IT8586E
V
+3VALW
V
+3VS
PCH_SMB_CLK
PCH
PCH_SMB_DATA +3VALW_PCH
EC SM Bus1 address
4
Device
X
X
X
0X16
Charger
0001 0010 b
Thermal
Sensor
PCH
X
X
X
X
X
V
X
+3VS
+3VALW_PCH
V
V
+3VS
+3VS
X
EC SM Bus2 address
X
V
+3VALW_PCH
TP
Module
X
X
X
charger
V
X
PCH SM Bus address
Address
Address
DDR DIMMA
1010 000Xb
1001_100xb
DDR DIMMB
1010 010Xb
VGA
0x41(default)
Wlan
Rsvd
PCH
need to update
Thermal Sensor NCT7718W
LAN
WLAN
Discrete GPU
X
Device
Device
Smart Battery
WLAN
WiMAX
SODIMM
1
2
3
4
5
6
Device
BTO Item
Not stuff
For 14" part
For 15" part
UMA SKU part
Discrete GPU SKU part
100M LAN Part
2
GIGA LAN Part
For AMD Jet GPU part
For AMD Topaz GPU part
For VRAM RankA part
For VRAM RankB part
ME part(connector, hole)
For support touch panel sku part
AOAC support part
Hynix 128Mx16 VRAM part
Hynix 256Mx16 VRAM part
Micron 128Mx16 VRAM part
Micron 256Mx16 VRAM part
Samsung 128Mx16 VRAM part
Samsung 256Mx16 VRAM part
Hynix 128Mx16 VRAM x4pcs sku
Micron 128Mx16 VRAM x4pcs sku
3
Samsung 128Mx16 VRAM x4pcs sku
Hynix 256Mx16 VRAM x4pcs sku
Micron 256Mx16 VRAM x4pcs sku
Samsung 256Mx16 VRAM x4pcs sku
Hynix 128Mx16 VRAM x8pcs sku
Micron 128Mx16 VRAM x8pcs sku
Samsung 128Mx16 VRAM x8pcs sku
Hynix 256Mx16 VRAM x8pcs sku
Micron 256Mx16 VRAM x8pcs sku
Samsung 256Mx16 VRAM x8pcs sku
Cost down part
Cost down part for BDW project
Single Rank VRAM sku
Dual Rank VRAM sku
4
Title
LC Future Center Secret Data
Security Classification
Issued Date
BOM Structure
@
14@
15@
UMA@
PX@
100M@
GIGA@
JET@
TOPAZ@
RANKA@
RANKB@
ME@
TS@
AOAC@
H2@
H4@
M2@
M4@
S2@
S4@
H2GX4@
M2GX4@
S2GX4@
H4GX4@
M4GX4@
S4GX4@
H2GX8@
M2GX8@
S2GX8@
H4GX8@
M4GX8@
S4GX8@
CD@
BCD@
SINGLE@
DUAL@
2015/02/27
2013/08/05
Deciphered Date
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
A
B
C
D
Sheet
E
3
of
59
5
4
3
UC1A
HDMI D2
D
HDMI D1
HDMI D0
HDMI CLK
34
34
34
34
34
34
34
34
HDMI_TX2HDMI_TX2+
HDMI_TX1HDMI_TX1+
HDMI_TX0HDMI_TX0+
HDMI_CLKHDMI_CLK+
HDMI_TX2HDMI_TX2+
HDMI_TX1HDMI_TX1+
HDMI_TX0HDMI_TX0+
HDMI_CLKHDMI_CLK+
C54
C55
B58
C58
B55
A55
A57
B57
C51
C50
C53
B54
C49
B50
A53
B53
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
2
1
HSW_ULT_DDR3L
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
DDI
EDP
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
C45
B46
A47
B47
CPU_EDP_TX0CPU_EDP_TX0+
CPU_EDP_TX1CPU_EDP_TX1+
CPU_EDP_TX0CPU_EDP_TX0+
CPU_EDP_TX1CPU_EDP_TX1+
33
33
33
33
D
C47
C46
A49
B49
A45
B45
CPU_EDP_AUX#
CPU_EDP_AUX
D20
A43
EDP_COMP
CPU_EDP_AUX#
CPU_EDP_AUX
1
RC1
33
33
+VCCIOA_OUT
2 24.9_0402_1%
+VCCIOA_OUT & EDP_COMP :
Trace Width: 20mil
Space: 25mil
Max length: 100mil
1 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@
+3VS
RPC19
DDPB_DATA
DDPB_CLK
HSW_ULT_DDR3L
UC1I
C
3
4
2
1
C
2.2K_0404_4P2R_5%
33
PCH_EDP_PWM
PCH_ENBKL
PCH_ENVDD
PCH_EDP_PWM
PCH_ENBKL
PCH_ENVDD
33
33
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
@ PAD
9
21,58
19
PXS_PWREN
PXS_RST#
PXS_PWREN
PXS_RST#
RC7
RC8
1
1
1
TC1
BOARD_ID3
GPIO52
PXS_PWREN_R
PXS_RST#_R
GPIO53
BOARD_ID3
OPT@2 1K_0402_5%
OPT@2 0_0402_5%
B8
A9
C6
U6
P4
N4
N2
AD4
U7
L1
L3
R5
L4
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
eDP SIDEBAND
DISPLAY
PCIE
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
B9
C9
D9
D11
DDPB_CLK
DDPB_DATA
DDPB_CLK
DDPB_DATA
34
34
*
DDPx_CTRLDATA
The signal has a weak internal pull-down.
H
Port is detected.
L
Port is not detected.
C5
B6
B5
A6
C8
A8
D6
HDMI_HPD
HDMI_HPD
34
EDP_HPD
9 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@
B
B
1
+3VS
RC9
1M_0402_5%
@
2
+3VS
RPC1
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
8
7
6
5
EDP_HPD
@
RC16 1
2
CPU_EDP_HPD
33
0_0402_5%
1
1
2
3
4
RC13
100K_0402_5%
10K_0804_8P4R_5%
2
+3VS
RC10
1
2
10K_0402_5%
GPIO52
RC11
1
2
10K_0402_5%
GPIO53
RC14
1
2
10K_0402_5%
PXS_PWREN_R
RC15
1
2
10K_0402_5%
PXS_RST#_R
@
A
A
RC17
2
RC18
1
@
1
100K_0402_5%
PXS_PWREN_R
2
10K_0402_5%
PXS_RST#_R
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
3
2
Sheet
1
4
of
59
5
4
3
2
1
HSW_ULT_DDR3L
UC1B
+1.05V_VCCST
D61
K61
N62
H_PROCHOT#_R
K63
1
H_PECI
D
2
RC19
62_0402_1%
44
H_PROCHOT#
44
56_0402_5%
H_PECI
1
2 RC20
1
2 RC21
10K_0402_5%
CPU_PROCPWRGD
MISC
D
JTAG
PROCHOT
C61
THERMAL
PROCPWRGD
2
SM_RCOMP_0
AU60
SM_RCOMP_1
AV60
SM_RCOMP_2
AU61
CPU_DRAMRST#_R AV15
SM_PG_CNTL1
AV61
14,15
CPU_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
1
100_0402_1%
2
1
RC24
SM_RCOMP_2
121_0402_1%
2
1
RC25
SM_RCOMP_1
200_0402_1%
2
1
RC26
SM_RCOMP_0
1
1
1
1
1
TC6
TC7
TC8
TC9
TC10
PAD
PAD
PAD
PAD
PAD
@
@
@
@
@
J60
H60
H61
H62
K59
H63
K60
J61
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
DDR3L
2 OF 19
CC1
0.1U_0402_25V6
2 EMC@
C
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
PWR
RC22
470_0402_5%
2
RC23 1
@
0_0402_5%
J62
K62
E60
E61
E59
F63
F62
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
1
+1.35V
PROC_DETECT
CATERR
PECI
BROADWELL-ULT-DDR3L_BGA1168
@
C
1
+3VALW
2
RC28
100K_0402_5%
CPU_DRAMPG_CNTL
55
+1.35V
1
B
RC3
1
2
1K_0402_5%
2
B
B
+1.35V
C
QC14
3
E
1
MMBT3904WH_SOT323-3
QC5
D
RC31 1
SM_PG_CNTL1
2 0_0402_5%
2
2
@
CD1
.1U_0402_10V6-K
@
S
1
3
PJA138K_SOT23-3
DDR_ODT
2
RD3
1
2 66.5_0402_1%
DDRB_ODT0
RD4
1
2 66.5_0402_1%
DDRB_ODT1
DDRB_ODT0
15
DDRB_ODT1
15
1
RC29
10K_0402_5%
@
G
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MCP (MISC,THERMAL,JATG)
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
5
of
59
5
4
DDRA_DQ[0..15]
D
15
14
DDRB_DQ[0..15]
DDRA_DQ[16..31]
C
15
DDRB_DQ[16..31]
DDRA_DQ2
DDRA_DQ4
DDRA_DQ7
DDRA_DQ6
DDRA_DQ1
DDRA_DQ3
DDRA_DQ0
DDRA_DQ5
DDRA_DQ15
DDRA_DQ10
DDRA_DQ9
DDRA_DQ8
DDRA_DQ14
DDRA_DQ11
DDRA_DQ13
DDRA_DQ12
DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRA_DQ19
DDRA_DQ20
DDRA_DQ18
DDRA_DQ17
DDRA_DQ23
DDRA_DQ22
DDRA_DQ21
DDRA_DQ16
DDRA_DQ28
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ24
DDRA_DQ29
DDRA_DQ31
DDRA_DQ30
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
UC1D
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
DDR CHANNEL A
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
DDRA_CLK0#
DDRA_CLK0
14
14
AU43
AW43
AY42
AY43
DDRA_CKE0
DDRA_CKE1
14
14
DDRA_CS0#
DDRA_CS1#
14
14
AP33
AR32
AY34
AW34
AU34
DDRA_RAS#
DDRA_W E#
DDRA_CAS#
AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_MA14
DDRA_MA15
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
DDRA_DQS#0
DDRA_DQS#1
DDRB_DQS#0
DDRB_DQS#1
DDRA_DQS#2
DDRA_DQS#3
DDRB_DQS#2
DDRB_DQS#3
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
DDRA_DQS0
DDRA_DQS1
DDRB_DQS0
DDRB_DQS1
DDRA_DQS2
DDRA_DQS3
DDRB_DQS2
DDRB_DQS3
AP49
AR51
AP51
@
C
F
C
L
5
DDRA_BS0#
DDRA_BS1#
DDRA_BS2#
DDRA_MA[0..15]
15
DDRA_DQ[32..47]
DDRB_DQ[32..47]
14
14
14
14
14
DDRA_DQ[48..63]
DDRA_DQS#[0..7]
DDRA_DQS[0..7]
DDRB_DQ[48..63]
14
14
15
DDRA_DQ37
DDRA_DQ36
DDRA_DQ38
DDRA_DQ35
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ39
DDRA_DQ41
DDRA_DQ47
DDRA_DQ44
DDRA_DQ43
DDRA_DQ45
DDRA_DQ40
DDRA_DQ42
DDRA_DQ46
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRA_DQ53
DDRA_DQ50
DDRA_DQ51
DDRA_DQ55
DDRA_DQ54
DDRA_DQ48
DDRA_DQ49
DDRA_DQ52
DDRA_DQ58
DDRA_DQ62
DDRA_DQ60
DDRA_DQ57
DDRA_DQ59
DDRA_DQ63
DDRA_DQ56
DDRA_DQ61
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
1
l
a
HSW_ULT_DDR3L
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_ODT0
SB_RAS
SB_WE
SB_CAS
n
e
4 OF 19
DDR CHANNEL B
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
i
t
SB_CS#0
SB_CS#1
d
i
f
n
15
o
C
DDRA_DQS[0..7]
3 OF 19
14
14
14
DDR_SM_VREFCA
DDR_SA_VREFDQ
DDR_SB_VREFDQ
DDRA_DQS#[0..7]
BROADWELL-ULT-DDR3L_BGA1168
14
AP32
SMVREF
WIDTH:20MIL
SPACING: 20MIL
B
A
2
HSW_ULT_DDR3L
UC1C
14
3
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_MA14
DDRB_MA15
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
DDRA_DQS#4
DDRA_DQS#5
DDRB_DQS#4
DDRB_DQS#5
DDRA_DQS#6
DDRA_DQS#7
DDRB_DQS#6
DDRB_DQS#7
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
DDRA_DQS4
DDRA_DQS5
DDRB_DQS4
DDRB_DQS5
DDRA_DQS6
DDRA_DQS7
DDRB_DQS6
DDRB_DQS7
DDRB_CLK0#
DDRB_CLK0
DDRB_CLK1#
DDRB_CLK1
15
15
15
15
DDRB_CKE0
DDRB_CKE1
15
15
DDRB_CS0#
DDRB_CS1#
15
15
DDRB_RAS#
DDRB_W E#
DDRB_CAS#
D
15
15
15
DDRB_BS0#
DDRB_BS1#
DDRB_BS2#
DDRB_MA[0..15]
15
15
15
15
C
B
DDRB_DQS#[0..7]
14
DDRB_DQS[0..7]
14
DDRB_DQS#[0..7]
DDRB_DQS[0..7]
15
15
BROADWELL-ULT-DDR3L_BGA1168
@
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
2013/08/05
MCP (DDR3L)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
4
3
2
1
Sheet
6
of
59
5
4
3
2
1
RTC_X1
RTC_X2
1 10M_0402_5%
YC1
1
D
CC4
15P_0402_50V8J
1
SATA0GP
SATA2GP
SATA3GP
2
32.768KHZ_12.5PF_202740-PG14
2
CC3
1U_0402_10V6K
VCCRTC
2
RC33
RC34
2
1
1
1
SRTC_RST#
RTC_RST#
2 20K_0402_1%
2 20K_0402_1%
CC5
18P_0402_50V8J
CC6
1U_0402_10V6K
1
1
1
2
2
2
RC32
RTC_RST#
44
UC1E
2
2
RC39
RC41
*
*
C
1
@
RTC_X1
RTC_X2
SM_INTRUDER#
INTVRMEN
SRTC_RST#
RTC_RST#
1 1M_0402_5%
1 330K_0402_5%
INTVRMEN
H Integrated VRM enable (Default)
L Integrated VRM disable
(INTVRMEN should always be pull high.)
43
43
43
43
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
HDA_SDIN0
43
44
HDA_SDOUT_AUDIO
ME_FLASH
2 33_0402_5%
2 33_0402_5%
2 33_0402_5%
HDA_BCLK
HDA_SYNC
HDA_RST#
HDA_SDIN0
RC45 1
RC46 1
2 33_0402_5%
2 0_0402_5%
HDA_SDOUT
@
2 1K_0402_5% HDA_SDOUT
TC24
TC25
TC26
TC28
TC30
@
@
@
@
@
1
1
1
1
1
PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
HDA_SDIN0
1
2
AW5
AY5
AU6
AV7
AV6
AU7
AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8
AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2
SML0_CLK
RC35
1
2 2.2K_0402_5%
SML0_DATA
RC36
1
2 2.2K_0402_5%
HSW_ULT_DDR3L
RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
RTC
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
RC42 1
RC43 1
RC44 1
HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY.
For EMI
D
+3VALW _PCH
VCCRTC
RC47
9
9
9
JCMOS1
SHORT PADS
@
CRYSTAL
1, Space 15MIL
2, No trace under crystal
3, Place on oppsosit side of MCP for temp influence
+3VALW _PCH
SATA0GP
SATA2GP
SATA3GP
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
AUDIO
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK
SATA
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD1
RSVD2
JTAGX
RSVD0
SATA_IREF
RSVD3
RSVD4
SATA_RCOMP
SATALED
JTAG
J5
H5
B15
A15
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
J8
H8
A17
B17
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
42
42
42
42
HDD
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
42
42
42
42
ODD
SMB_ALERT#
SML0_ALERT#
SML1_ALERT#
SMB_ALERT#
SML0_ALERT#
SML1_ALERT#
9
9
9
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
SATA0GP
ODD_DETECT#
SATA2GP
SATA3GP
A12
L11
K10
C12 SATA_RCOMP RC48
U3
ODD_DETECT#
9,42
IREF&RCOMP
Width: 12-15Mil
Space:12Mil
Length: 500Mil
+1.05VS_PSATA3PLL
2
C
1 3.01K_0402_1%
CC7
10P_0402_50V8J
EMC_NS@
5 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@
HSW_ULT_DDR3L
2 15_0402_5%
2 0_0402_5%
SPI_CLK_R
SPI_CS0#_R
@
SPI_SI
SPI_SO
SPI_SI
SPI_SO
RC52 1
RC53 1
2 15_0402_5%
2 15_0402_5%
B
SPI_SI_R
SPI_SO_R
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
SMBUS
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
SPI
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST
C-LINK
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
SMB_ALERT#
PCH_SMB_CLK
PCH_SMB_DATA
SML0_ALERT#
SML0_CLK
SML0_DATA
SML1_ALERT#
PCH_SML1_CLK
PCH_SML1_DAT
AF2
AD2
AF4
DIMM1, DIMM2, NGFF
+3VALW _PCH
+3VS
+3VS
RPC20
2.2K_0404_4P2R_5%
1
2
2
1
7 OF 19
QC2A
6
1
SMB_CLK_S3
15,40
G
2N7002KDW H_SOT363-6
5
D
@
S
PCH_SMB_CLK
BROADWELL-ULT-DDR3L_BGA1168
B
RPC24
2.2K_0404_4P2R_5%
2
RC50 1
RC51 1
LPC
G
44
44
SPI_CLK
SPI_CS0#
SPI_CLK
SPI_CS0#
LAD0
LAD1
LAD2
LAD3
LFRAME
3
4
44
44
AU14
AW12
AY12
AW11
AV12
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
4
3
UC1G
32,44
32,44
32,44
32,44
32,44
QC2B
3
4
S
PCH_SMB_DATA
SMB_DATA_S3
D
+3V_SPI
1
1
+3V_SPI
RC61
1K_0402_5%
2
2
RC60
1K_0402_5%
UC3
SPI_CS0#
1
SPI_SO
2
SPI_W P#
3
SPI_W P#
4
SPI_HOLD#
15,40
2N7002KDW H_SOT363-6
CS#
DO
WP#
VCC
HOLD#
CLK
GND
DI
8
7
SPI_HOLD#
6
SPI_CLK
5
SPI_SI
1
CC8
.1U_0402_10V6-K
2
GPU, EC, Thermal Sensor
+3VALW _PCH
+3VS
G
1
2
RPC25
2.2K_0404_4P2R_5%
2
4
3
W 25Q64FVSSIQ_SO8
6
1 @
EC_SMB_CK2
2N7002KDW H_SOT363-6
19,44
5
D
QC3A
S
PCH_SML1_CLK
A
G
A
+3V_SPI
PCH_SML1_DAT
QC3B
3
4
@
EC_SMB_DA2
D
2
RC1711
@
0_0402_5%
S
+3VALW _PCH
19,44
2N7002KDW H_SOT363-6
*
Issued Date
Title
LC Future Center Secret Data
Security Classification
+3V_SPI
1. If support DS3, connect to +3VS and don't support EC mirror code;
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
2015/02/27
Deciphered Date
2013/08/05
MCP (RTC&AUDIO&SATA&SMBUS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
7
of
59
5
4
3
2
1
2
RC71
1 1M_0402_5%
YC2
9
9
9
PCIE_CLKREQ1#
PCIE_CLKREQ0#
PCIE_CLKREQ5#
PCIE_CLKREQ1#
PCIE_CLKREQ0#
PCIE_CLKREQ5#
2
XTAL24_IN
CC12
4.7P_0402_50V8B
D
9
9
LAN
PCIE CLK3
WLAN 40
CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#
40
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#
9,40
PCIE CLK4
GPU
19
19
19
CLK_PCIE_GPU#
CLK_PCIE_GPU
GPU_CLKREQ#
PCIE_CLKREQ0#
C43
C42
U2
PCIE_CLKREQ1#
B41
A41
Y5
CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#
C41
B42
AD1
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#
B38
C37
N1
CLK_PCIE_GPU#
CLK_PCIE_GPU
GPU_CLKREQ#
A39
B39
U5
PCIE_CLKREQ5#
B37
A37
T2
+3VS
C
RC120
1
2 10K_0402_5%
OSC2
OSC1
GND2
XTAL24_OUT
3
4
1
24MHZ_6PF_7V24000032
1
2
CC11
3.3P_0402_50V8-C
D
HSW_ULT_DDR3L
UC1F
37
37
9,37
PCIE CLK2
GND1
2
SYS_RESET#
PM_CLKRUN#
SYS_RESET#
PM_CLKRUN#
1
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
XTAL24_IN
XTAL24_OUT
RSVD5
RSVD6
DIFFCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLOCK
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
SIGNALS
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
A25
B25
XTAL24_IN
XTAL24_OUT
K21
M21
C26
DIFFCLK_BIASREF
+1.05VS_PLPTCLKPLL
2
1
RC72
C35
C34
AK8
AL8
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
AN15
AP15
CLK_PCI_EC_R
CLK_PCI_TPM_R
RC73
RC183
3.01K_0402_1%
2
2
1 22_0402_5%
1 22_0402_5%
TPM@
DIFFCLK_BIASREF
Width: 12-15Mil
Space:12Mil
Length: 500Mil
CLK_PCI_EC
CLK_PCI_TPM
44
32
B35
A35
RPC5
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
8
7
6
5
1
2
3
4
10K_0804_8P4R_5%
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
C
GPU_CLKREQ#
6 OF 19
BROADWELL-ULT-DDR3L_BGA1168
VCCRTC
1
@
+3VALW_PCH
RC74
1
2 10K_0402_5%
AC_PRESENT_R
RC76
1
2 10K_0402_5%
WAKE#
RC78
1
2 10K_0402_5%
SUSWARN#_R
RC90
1
2 10K_0402_5%
PCH_GPIO72
2
RC77
330K_0402_5%
1
DSWODVREN
SYSTEM POWER MANAGEMENT
Reserve for DS3
SUSWARN#_R
44
10,44
19,32,37,40,44
B
SYS_PWROK
PCH_PWROK
PLT_RST#
44
EC_RSMRST#
44
PBTN_OUT#
CC104 1
EMC_NS@
PCH_PWROK
2
1000P_0402_50V7K
CC103 1
EMC_NS@
PCH_DPWROK_R
2
1000P_0402_50V7K
RC80
330K_0402_5%
@
HSW_ULT_DDR3L
2
UC1H
RC79
1
@
2 0_0402_5%
RC139
RC126
RC83
RC84
1
1
1
1
@
@
@
@
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
RC85
1
@
2 0_0402_5%
RC87
1
@
2 0_0402_5%
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK_R
APWROK
PLT_RST#_R
AK2
AC3
AG2
AY7
AB5
AG7
PCH_RSMRST#_R
SUSWARN#_R
PBTN_OUT#_R
AC_PRESENT_R
PCH_GPIO72
AW6
AV4
AL7
AJ8
AN4
AF3
AM5
SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST
DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
AW7
AV5
AJ5
DSWODVREN
PCH_DPWROK_R
WAKE#
V5
AG4
AE6
AP5
PM_CLKRUN#
AJ6
AT4
AL5
AP4
AJ7
PM_SLP_S4#_R
PM_SLP_S3#_R
RC182
RC82
1
1
@
@
2 0_0402_5%
2 0_0402_5%
EC_RSMRST#
PCIE_WAKE#
44
*
DSWODVREN - On Die DSW VR Enable
H Enable
L Disable
B
SUSCLK
PM_SLP_S5#
RC140
RC141
1
1
@
@
2 0_0402_5%
2 0_0402_5%
PM_SLP_S5#
44
PM_SLP_S4#
PM_SLP_S3#
44
44
8 OF 19
BROADWELL-ULT-DDR3L_BGA1168
CC101 1
EMC@
RC91 1
@
2 1000P_0402_50V7K
2 10K_0402_5%
SYS_PWROK
44
RC88
AC_PRESENT
1
@
2 0_0402_5%
AC_PRESENT_R
RPC21
1
2
A
4
3
PCH_PWROK
PCH_RSMRST#_R
10K_0404_4P2R_5%
2
CC142 1
EMC_NS@
1000P_0402_50V7K
A
1 RC92
PLT_RST#_R
100K_0402_1% 2
@
1 RC94
PCH_DPWROK_R
1K_0402_5%
1
@
2 RC95
SUSCLK
10K_0402_5%
2
@
1 RC105
GPU_CLKREQ#
100K_0402_5% 2
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MCP (Clock,PM)
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Monday, May 11, 2015
Sheet
1
8
of
59
5
4
3
2
1
+3VALW_PCH
+3VS
RPC8
8
7
6
5
PCH_GPIO47
PCH_GPIO28
ODD_EN
PCH_GPIO56
1
2
3
4
10K_0804_8P4R_5%
RPC9
8
7
6
5
PCH_GPIO10
SML0_ALERT#
USB_OC0#
PCH_GPIO44
1
2
3
4
SML0_ALERT#
7
10K_0804_8P4R_5%
RPC17
1
2
3
4
@
PCH_GPIO8
USB_OC3#
USB_OC1#
SMB_ALERT#
8
7
6
5
44
EC_SMI#
EC_SMI#
RC111
1
2
SMB_ALERT#
7
RPC22
PCH_GPIO58
PCH_GPIO59
SML1_ALERT#
1
2
3
4
43
SML1_ALERT#
PCH_BEEP
7
SERIAL IO
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
PCH_GPIO83
BOARD_ID1
PCH_GPIO85
PCH_GPIO86
PCH_BT_OFF#
PCH_WLAN_OFF#
PCH_GPIO89
PCH_GPIO90
PCH_GPIO91
PCH_GPIO92
PCH_GPIO93
PCH_GPIO94
PCH_GPIO0
PCH_GPIO1
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
PCH_GPIO6
PCH_GPIO7
RC112 1
PCH_GPIO64
PCH_GPIO65
KBRST#
SERIRQ
149.9_0402_1%
TC41
2
2
1
1
2
RC108
10K_0402_5%
14@
RC109
10K_0402_5%
@
RC123
10K_0402_5%
@
RC185
10K_0402_5%
@
D
OPI_RCOMP
Width 20Mil
Space 15Mil
Length 500Mil
PCH_BT_OFF#
PCH_WLAN_OFF#
2 0_0402_5%
EC_SCI#
@
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
1
X
X
X
X
DIS SKU
UMA SKU
Description
40
40
0
X
X
X
X
X
1
X
X
X
15" SKU
X
0
X
X
X
14"
X
X
0
0
0
MS2G@: K4B4G1646Q-HYK0
X
X
0
0
1
MH2G@: H5TC4G63CFR-PBA
X
X
0
1
0
MM2G@: MT41K256M16LY-107:N
X
X
0
1
1
MS4G@: K4B8G1646Q-MYK0
X
X
1
0
0
MH4G@: H5TC8G63AMR-PBA
X
X
1
0
1
MM4G@: MT41K512M16HA-125:A
SKU
44
PCH_GPIO67
CMOS_ON#
PCH_GPIO69
10 OF 19
10K_0804_8P4R_5%
RC107
10K_0402_5%
UMA@
44
32,44
2
H_THRMTRIP#_R
KBRST#
SERIRQ
OPI_COMP
RC106 2
1 @
RC184
10K_0402_5%
@
1
AM3
AM2
P2
C4
L2
N5
V2
GPIO
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
D60
V4
T4
AW15
AF20
AB21
2
PCH_GPIO9
PCH_GPIO10
PCH_GPIO33
PCH_GPIO70
PCH_GPIO38
BOARD_ID2
PCH_BEEP
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
CPU/
MISC
THRMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD7
RSVD8
RC121
10K_0402_5%
@
1
AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
RC102
10K_0402_5%
@
2
PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
PCH_GPIO59
PCH_GPIO44
PCH_GPIO47
VGA_PWRGD
BOARD_ID4
PCH_GPIO50
PCH_GPIO71
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46
0_0402_5%
10K_0804_8P4R_5%
8
7
6
5
BOARD_ID0
ODD_DA#
ODD_EN
DS3_WAKE#
PCH_GPIO28
PCH_GPIO26
P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3
2
PCH_GPIO76
PCH_GPIO8
PCH_GPIO12
1
PCH_GPIO45
PCH_GPIO46
USB_OC2#
PCH_GPIO14
1
2
3
4
10K_0804_8P4R_5%
+3VS
BOARD_ID3
1
4
RPC7
8
7
6
5
RC101
10K_0402_5%
15@
1
2
RC104
1K_0402_5%
10K_0804_8P4R_5%
D
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
1
HSW_ULT_DDR3L
UC1J
RC100
10K_0402_5%
OPT@
+1.05V_VCCST
1
@ 2
2
PCH_GPIO13
PCH_GPIO57
PCH_GPIO26
PCH_GPIO9
1
2
3
4
1
1
RPC6
8
7
6
5
2
+3VALW_PCH
1
PCH_GPIO14
RC96 1
@
2
0_0402_5%
EC_LID_OUT#
CC102
44
.01U_0402_16V7-K
PCH_GPIO12
DS3_WAKE#
PCH_GPIO25
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
@
2
H_THRMTRIP#_R
1
1
1
RC97
RC98
RC99
BROADW ELL-ULT-DDR3L_BGA1168
@
RPC2
C
8
7
6
5
1
2
3
4
SERIRQ
PCIE_CLKREQ0#
SATA0GP
ODD_DETECT#
PCIE_CLKREQ0#
SATA0GP
ODD_DETECT#
19
7,42
10K_0804_8P4R_5%
19
RPC3
1
2
3
4
8
7
6
5
C
8
7
PCH_GPIO83
PCH_GPIO92
PCH_GPIO85
PCIE_CRX_GTX_N[0..3]
PCIE_CRX_GTX_P[0..3]
19
PCIE_CTX_C_GRX_N[0..3]
19
PCIE_CTX_C_GRX_P[0..3]
UC1K
HSW_ULT_DDR3L
10K_0804_8P4R_5%
RPC4
1
2
3
4
8
7
6
5
PCH_GPIO38
PCH_BT_OFF#
WLAN_CLKREQ#
PCH_GPIO33
WLAN_CLKREQ#
8,40
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P0
.1U_0402_10V6-K
.1U_0402_10V6-K
OPT@ 1
OPT@ 1
2 CC16
2 CC14
.1U_0402_10V6-K
.1U_0402_10V6-K
OPT@ 1
OPT@ 1
2 CC15
2 CC17
10K_0804_8P4R_5%
GPU PCIE5
RPC10
8
7
6
5
1
2
3
4
LAN_CLKREQ#
SYS_RESET#
SATA3GP
PCH_GPIO71
LAN_CLKREQ#
SYS_RESET#
SATA3GP
8,37
8
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P1
7
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P0
F10
E10
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P0
C23
C22
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P1
F8
E8
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P1
B23
A23
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P2
H10
G10
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P2
B21
C21
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3
E6
F6
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P3
B22
A21
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
G11
F11
10K_0804_8P4R_5%
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P2
RPC11
8
7
6
5
B
1
2
3
4
ODD_DA#
PCIE_CLKREQ5#
PCH_GPIO50
PCH_GPIO76
PCIE_CLKREQ5#
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P3
RPC12
1
2
3
4
PCH_GPIO90
PCH_GPIO2
PCH_GPIO93
PCH_GPIO91
LAN
RPC13
1
2
3
4
PCH_GPIO3
PCH_GPIO1
PCH_GPIO94
PCH_GPIO4
WLAN
37
37
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
37
37
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3
40
40
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
40
40
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4
PCIE3
10K_0804_8P4R_5%
8
7
6
5
OPT@ 1
OPT@ 1
2 CC18
2 CC19
8
10K_0804_8P4R_5%
8
7
6
5
.1U_0402_10V6-K
.1U_0402_10V6-K
PCIE4
.1U_0402_10V6-K
.1U_0402_10V6-K
CC22 1
CC23 1
CC24 1
CC25 1
OPT@ 1
OPT@ 1
2 CC20
2 CC21
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
C29
B30
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
F13
G13
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
B29
A29
G17
F17
10K_0804_8P4R_5%
C30
C31
RPC14
8
7
6
5
1
2
3
4
PCH_GPIO5
PCH_GPIO69
CMOS_ON#
PCH_GPIO70
F15
G15
B31
A31
10K_0804_8P4R_5%
PERN5_L0
PERP5_L0
USB2N0
USB2P0
PETN5_L0
PETP5_L0
USB2N1
USB2P1
PERN5_L1
PERP5_L1
USB2N2
USB2P2
PETN5_L1
PETP5_L1
USB2N3
USB2P3
PERN5_L2
PERP5_L2
USB2N4
USB2P4
PETN5_L2
PETP5_L2
USB2N5
USB2P5
PERN5_L3
PERP5_L3
USB2N6
USB2P6
PETN5_L3
PETP5_L3
USB2N7
USB2P7
PERN3
PERP3
PETN3
PETP3
USB3RN1
USB3RP1
PCIE
USB
USB3TN1
USB3TP1
PERN4
PERP4
USB3RN2
USB3RP2
PETN4
PETP4
USB3TN2
USB3TP2
8
7
6
5
1
2
3
4
+1.05VS_PUSB3PLL
RC119
2
1 3.01K_0402_1%
10K_0804_8P4R_5%
PCIE_RCOMP&PCIE_IREF
Width 12~15Mil
Space >12Mil
Length 500Mil
RPC16
8
7
6
5
A
1
2
3
4
PCH_GPIO67
PCH_GPIO64
PCH_GPIO6
PCH_WLAN_OFF#
PCIE_RCOMP
E15
E13
A27
B27
USB20_N0
USB20_P0
AR7
AT7
USB20_N1
USB20_P1
USB20_N0
USB20_P0
41
41
USB20_N1
USB20_P1
41
41
USB20_N3
USB20_P3
30
30
USB20_N5
USB20_P5
33
33
USB20_N6
USB20_P6
40
40
LEFT USB (2.0)
LEFT USB (3.0)
AR8
AP8
AR10
AT10
USB20_N3
USB20_P3
Card reader
AM15
AL15
AM13
AN13
USB20_N5
USB20_P5
AP11
AN11
USB20_N6
USB20_P6
Camera
BT
AR13
AP13
B
G20
H20
USB30_RX_N1
USB30_RX_P1
C33
B34
USB30_TX_N1
USB30_TX_P1
USB30_RX_N1
USB30_RX_P1
41
41
PCH_GPIO86
LEFT USB (3.0)
USB30_TX_N1
USB30_TX_P1
41
41
RC116
2
@
1 1K_0402_5%
@
1 1K_0402_5%
GPIO86, Internal PD
1: LPC
*0: SPI
E18
F18
B33
A33
PERN1/USB3RN3
PERP1/USB3RP3
+3VS
PETN1/USB3TN3
PETP1/USB3TP3
USBRBIAS
USBRBIAS
RSVD11
RSVD12
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
RPC15
PCH_GPIO7
PCH_GPIO65
PCH_GPIO0
PCH_GPIO89
AN8
AM8
RSVD9
RSVD10
PCIE_RCOMP
PCIE_IREF
AJ10
AJ11
AN10
AM10
USBRBIAS
AL3
AT1
AH2
AV3
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
RC118
2
1
22.6_0402_1%
USB_OC1#
PCH_BEEP
USBRBIAS
Width 20Mil
Space 15Mil
Length 500Mil
RC117
2
GPIO81, No Reboot, Internal PD
1: Enabled No Reboot Mode
*0: Disable No Reboot Mode
41
11 OF 19
BROADW ELL-ULT-DDR3L_BGA1168
@
A
10K_0804_8P4R_5%
RPC18
1
2
3
4
8
7
6
5
PCIE_CLKREQ1#
KBRST#
SATA2GP
PM_CLKRUN#
PCIE_CLKREQ1#
8
SATA2GP
7
PM_CLKRUN#
8
Issued Date
1
2 10K_0402_5% VGA_PWRGD
Title
LC Future Center Secret Data
Security Classification
10K_0804_8P4R_5%
RC181
2015/02/27
Deciphered Date
2013/08/05
MCP (GPIO,USB,PCIE)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
5
4
3
2
1
Sheet
9
of
59
5
4
3
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
D
CPU_CORE
2
1
2
59
CPU_SVID_ALERT#_R
CPU_SVID_CLK_R
CPU_SVID_DAT_R
VCCST_PW RGD
CPU_VR_ON
CPU_VR_READY
CPU_VR_ON
L62
N63
L63
B59
F60
C59
+1.05VS
RC129
2
@
RC130
1
1
1
VCCST(0.1A)
1
2
@
0_0402_5%
1
CC39
22U_0805_6.3V6M
BCD@
SVID
1, Stripline Line, No More Than 6000Mil
2, Alert# Route Between CLK and Data
3, CLK Length<Data Length<CLK Length + 2000Mil
4, Space at least 18Mil
59
CPU_SVID_CLK
B
59
CPU_SVID_DAT
2
AB57
AD57
AG57
C24
C28
C32
1
VCCST1
VCCST2
VCCST3
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
2
1
2
1
@2
1
2
1
2
1
+
2
@
BCD@
1.35V_CPU(1.4A)
HW 4PCS 2.2UF CAP Mounted
HW 6PCS 10UF CAP Mounted
PWR 2PCS 470U Near VR Output
+1.35V_CPU
1
2
1
2
C
For RF
12 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@
For RF
1
CC42
.1U_0402_10V6-K
@
2
2
1
2
RC132
130_0402_1%
1
CPU_SVID_ALERT#
CC40
1U_0402_10V6K
BCD@
+1.05VS
RC131
75_0402_1%
59
2
AC22
AE22
AE23
CPU_CORE
1
33P_0402_50V8J
@
CC2
LC1
2
@
+1.05V_VCCST
1
CD@
@
+1.05VS
2
33P_0402_50V8J
C
1
33P_0402_50V8J
2
1
10K_0402_5%
VSS344
PWR_DEBUG
VSS345
RSVD_TP1
RSVD_TP2
RSVD_TP3
RSVD_TP4
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
D
For cost down, change to X5R.
CC38
@ TC53
@ TC54
@ TC55
HSW ULT POWER
2
BCD@
CC37
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
PW R_DEBUG
1 150_0402_1%
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
1
CC41
330U_2.5V_M
1
2
CC33
10U_0603_6.3V6M
CC36
4.7U_0603_10V6-K
@
VCC_SENSE
RSVD17
VCCIO_OUT
VCCIOA_OUT
RSVD18
RSVD19
RSVD20
1
CC32
10U_0603_6.3V6M
+VCCIOA_OUT
VCC1
RSVD15
RSVD16
2
CC31
10U_0603_6.3V6M
E63
AB23
A59
E20
AD23
AA23
AE59
CD@
1
CC35
10U_0603_6.3V6M
CPU_VCC_SENSE
1
2
@
0_0402_5%
2
CC30
10U_0603_6.3V6M
59
F59
N58
AC58
RC127
100_0402_1%
RC128
1
CC34
10U_0603_6.3V6M
VCC_SENSE
Length Match: <25Mil
Space: More Than 25Mil
GND Reference
+VCCIO_OUT
CPU_CORE
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
CC29
2.2U_0603_10V6-K
2
+1.35V_CPU
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
CC28
2.2U_0603_10V6-K
2
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
CC27
2.2U_0603_10V6-K
@
1
JUMP_43X79
RSVD13
RSVD14
1
CC26
2.2U_0603_10V6-K
JC1
1
L59
J58
+1.35V_CPU
Need short
CPU_CORE
HSW_ULT_DDR3L
UC1L
+1.35V
2
RC133
2
1 43_0402_5%
CPU_SVID_ALERT#_R
RC134
1
@
2 0_0402_5%
CPU_SVID_CLK_R
RC135
1
@
2 0_0402_5%
CPU_SVID_DAT_R
B
2
CPU_VR_ON
+1.05V_VCCST
2
RC146
10K_0402_5%
1
RC137
1K_0402_5%
1
2
+3VALW
1
QC6B
2N7002KDW H_SOT363-6
@
2
@
1
0_0402_5%
2
G
1
2
CC46
0.01U_0402_16V7K
@
S
D
4
6
RC138
VR_CPU_PW ROK
RC155
1
QC6A
2N7002KDW H_SOT363-6
@
CPU_VR_READY
2 0_0402_5%
8,44
1
2
1
CC140
1000P_0402_50V7K
@
2
CC141
100P_0402_50V8J
@
S
1
PCH_PW ROK
VCCST_PW RGD
D
5
G
8,44
44,59
VCCST_PW RGD
3
RC136
10K_0402_5%
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
MCP (Power)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
2
Sheet
1
10
of
59
5
4
3
2
1
+3VALW _PCH
VCCHSIO
Y20
AA21
W21
+1.05VS_POPIPLL
VCCRTC
HSIO
RTC
VCCSUS3_3[5]
VCCRTC
DCPRTC
VCCSPI
OPI
1U_0402_10V6K
1
2 CC59 +1.05VS_DCPSUS3
J13
@
1U_0402_10V6K
1
2 CC60 +1.05VS_DCPSUS2
AH13
USB3
DCPSUS3
VCCHDA
VRM
CORE
+3VALW _PCH
VCCSUS3_3[1:5]
VCCDSW 3_3
+3VS
1
2
VCC3_3[1:4]
41mA
GPIO/LPC
VCCTS1_5
VCC3_3[3]
VCC3_3[4]
THERMAL SENSOR
+1.05VS_PLPTVCC1P05
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
+1.05VS_DCPSUS1
VCCTS1_5
1
2
CC76
1U_0402_10V6K
CC75
1U_0402_10V6K
2
+3VALW _PCH
VCCCLK[1]
VCCCLK[2]
VCCACLKPLL
VCCCLK[3]
VCCCLK[4]
VCCCLK[5]
RSVD31
RSVD32
RSVD33
VCCSUS3_3[3]
VCCSUS3_3[4]
SERIAL IO
VCCSDIO[1]
VCCSDIO[2]
U8
T9
DCPSUS4
USB2
VCCHDA
1 @
2
1U_0402_10V6K
1
@
VCCSDIO
2
17mA
1U_0402_10V6K
2
1 @
CC73
+1.05VS_DCPSUS4
1
AC20
AG16
AG17
1
1
2
1
2
1
1
2
BCD@
2
1
@
C
CC77
1U_0402_10V6K
2
1
@
0_0402_5%
2
2
+1.05VS
+3VS
BROADWELL-ULT-DDR3L_BGA1168
RC152
+1.05VS
2
AB8
1
3mA
13 OF 19
+3VALW _PCH
VCCDSW 3_3
1
CD@
+1.05VS
RSVD34
VCC1_05[8]
VCC1_05[9]
CD@
2
1
@
0_0402_5%
CC66
LPT LP POWER
SUS OSCILLATOR
D
2
1U_0402_10V6K
2
1
CC61
+PCH_DCPSUSBYP
+1.5VS
J15
K14
K16
1
CC74
1U_0402_10V6K
J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21
+1.05VS_PLPTCLKPLL
1
RC150
1
658mA
+3VS
+1.05VS
C
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCDSW3_3
VCC3_3[1]
VCC3_3[2]
VCCASW[1:5]
2
CC72
0.1U_0402_10V7K
2
AC9
AA9
AH10
V8
W9
114mA
CC71
22U_0805_6.3V6M
1
CC70 @
1U_0402_10V6K
2
CC67
22U_0805_6.3V6M
1
65mA
VCCDSW
AG14
AG13
2
22U_0805_6.3V6M
CC69
@
VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]
VCC1_05[7]
DCPSUSBYP[1]
DCPSUSBYP[2]
VCCASW[3]
VCCASW[4]
VCCASW[5]
DCPSUS1[1]
DCPSUS1[2]
HDA
DCPSUS2
0.1U_0402_10V7K
10U_0603_6.3V6M
CC65
AH14
2
1U_0402_10V6K
CC68
2
CC62
1U_0402_10V6K
1
11mA
18mA
1mA
1
1U_0402_10V6K
CC64
VCCHDA
VCCSPI
Y8
2
1U_0402_10V6K
CC63
VCCHDA
CC52
+1.05VS
VCCASW[1]
VCCASW[2]
@
VCCRTC
+DCPRTC
VCCSPI
SPI
RSVD30
VCCAPLL[1]
VCCAPLL[2]
AH11
AG10
AE7
1U_0402_10V6K
CC57
+1.05VS_PUSB3PLL
+1.05VS_PSATA3PLL
CC50
1U_0402_10V6K
1
0.1U_0402_10V7K
CC56
BCD@
1.741A
VCCHSIO[1]
VCCHSIO[2]
VCCHSIO[3]
VCC1_05[1]
VCC1_05[2]
VCCUSB3PLL
VCCSATA3PLL
CC58 @
0.1U_0402_10V7K
2
VCC1_05[1:9]
K9
L10
M9
N8
P9
B18
B11
0.1U_0402_10V7K
CC55
2
1
CC54
1U_0402_10V6K
2
1
CC51
1U_0402_10V6K
D
CC53
1U_0402_10V6K
1
+1.05VS
1.838A
2
HSW_ULT_DDR3L
UC1M
+1.05VS
+1.05VS
+1.05VS_PUSB3PLL
+1.05VS
+1.05VS_PLPTVCC1P05
+3VS
1
LC2
2
0_0603_5%
+1.05VS_PUSB3PLL
41mA
1
2
CC78
22U_0805_6.3V6M
@
1
CC79
22U_0805_6.3V6M
2
1
+1.05VS_PLPTVCC1P05
1
2
0_0603_5%
LC3
1
CC80
1U_0402_10V6K
1
CC81
22U_0805_6.3V6M
2 BCD@
2
185mA
2
1
CC100
22U_0805_6.3V6M
1
CC82
22U_0805_6.3V6M
2 BCD@
2
1
CC83
22U_0805_6.3V6M
2
CC84
1U_0402_10V6K
+3V_SPI
0_0402_5% 2
@
1
RC154
VCCSPI
+1.05VS_PSATA3PLL
B
LC4
1
2
0_0603_5%
+1.05VS_PSATA3PLL
2
CC90 1
2 0.47U_0402_25V6K
CC85
22U_0805_6.3V6M
1
2
CC86
22U_0805_6.3V6M
@
1
+1.05VS_PLPTCLKPLL
31mA
1
2
0_0603_5%
LC5
1
VCCDSW 3_3
+1.05VS_PLPTCLKPLL
42mA
B
1
CC87
1U_0402_10V6K
2
2
CC88
22U_0805_6.3V6M
1
1
1
CC95
22U_0805_6.3V6M
2 BCD@
CC98
22U_0805_6.3V6M
2 BCD@
2
1
CC99
22U_0805_6.3V6M
2
CC89
1U_0402_10V6K
+PCH_DCPSUSBYP
+1.05VS_POPIPLL
For Intel recommend, place one 0.47uF
capacitor to address temporary inrush
current.(DOC.489999)
LC6
1
2
1
@
2 0_0603_5%
CC91
33P_0402_50V8J
@
+1.05VS_POPIPLL
57mA
1
1
1
CC92
47U_0805_4V6-M
2@
CC93
47U_0805_4V6-M
2@
2
CC94
1U_0402_10V6K
For RF
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
MCP (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
2
Sheet
1
11
of
59
4
D
C
B
HSW_ULT_DDR3L
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
UC1O
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
2
1
HSW_ULT_DDR3L
15 OF 19
BROADWELL-ULT-DDR3L_BGA1168
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
D
UC1P
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
HSW_ULT_DDR3L
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
16 OF 19
BROADWELL-ULT-DDR3L_BGA1168
VSS338
VSS339
VSS340
VSS_SENSE
VSS341
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
C
RC158
1
@
2 0_0402_5%
CPU_VSS_SENSE
B
59
2
UC1N
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
3
RC159
100_0402_1%
@
VSS_SENSE
Length Match: No More Than 25Mil
Space: More Than 25Mil
GND Reference
1
5
@
14 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MCP (VSS)
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
12
of
59
5
4
3
UC1Q
TC70
D
TC73
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
TP_DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
@ 1
@ 1
DC_TEST_C1_C2
AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2
2
1
HSW_ULT_DDR3L
DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
17 OF 19
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
A3
A4
DC_TEST_A3_B3
TP_DC_TEST_A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
TP_DC_TEST_A60
DC_TEST_A61_B61
TP_DC_TEST_A62
TP_DC_TEST_AV1
TP_DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_AW63
1 @
TC71
1 @
TC72
1 @
1 @
1 @
TC74
TC75
TC76
1 @
TC77
D
BROADWELL-ULT-DDR3L_BGA1168
@
UC1R
AT2
AU44
AV44
D15
F22
H22
J21
C
HSW_ULT_DDR3L
RSVD42
RSVD43
RSVD44
RSVD45
RSVD35
RSVD36
RSVD37
RSVD38
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD39
RSVD40
RSVD41
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
C
18 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@
UC1S
B
RC163
2
TC96
TC98
TC99
TC100
TC102
TC104
TC106
TC108
TC109
TC111
TC113
TC114
TC116
TC117
TC119
TC120
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
TC123
TC124
TC125
TC127
@
@
@
@
1
1
1
1
CFG16
CFG18
CFG17
CFG19
AA62
U63
AA61
U62
1 49.9_0402_1%
CFG_RCOMP
V63
A5
CFG_RCOMP&TD_IREF
Width 20Mil
Space 15Mil
Length 500Mil
2
RC166
TD_IREF
1
8.2K_0402_1%
E1
D1
J20
H18
B12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
HSW_ULT_DDR3L
RSVD_TP5
RSVD_TP6
RSVD_TP7
RSVD_TP8
RSVD58
RSVD_TP9
RSVD_TP10
RSVD_TP11
RESERVED
RSVD59
RSVD60
RSVD61
PROC_OPI_RCOMP
CFG16
CFG18
CFG17
CFG19
RSVD62
RSVD63
CFG_RCOMP
VSS342
VSS343
RSVD53
RSVD64
RSVD65
RSVD54
RSVD55
RSVD56
RSVD57
TD_IREF
AV63
AU63
1 @
1 @
TC97
TC101
C63
C62
B43
1 @
1 @
1 @
TC103
TC105
TC107
A51
B51
1 @
1 @
TC110
TC112
L60
1 @
TC115
CFG3
CFG4
PROC_OPI_COMP
2
@
1 1K_0402_1%
CFG3
*1: Disable
0: Enable, Set DFX Enabled BIT
In Debug Interface MSR
N60
W23
Y22
AY15
RC160
RC162
2
1
49.9_0402_1%
AV62
D58
PROC_OPI_RCOMP
Width 20Mil
Space 15Mil
Length 500Mil
RC161
2
1 1K_0402_1%
B
CFG4
*L: eDP enable
H: eDP disable
P22
N21
P20
R20
CFG0
RC164
2
@
1 1K_0402_1%
CFG1
RC165
2
@
1 1K_0402_1%
CFG8
RC167
2
@
1 1K_0402_1%
CFG9
RC168
2
@
1 1K_0402_1%
CFG10
RC169
2
@
1 1K_0402_1%
19 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MCP (OTHER)
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
13
of
59
5
4
3
2
1
Signal voltage level = 0.675 V
PLACE TWO 4.7K RESISTORS CLOSE TO
DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
Decoupling caps are needed; one 0.1μF placed close to VREF pins
U15
D
DDRA_DQ[63:0]
6
DDRA_MA[15:0]
6
DDRA_DQS[7:0]
6
DDRA_DQS#[7:0]
6
6
6
6
DDRA_BS0#
DDRA_BS1#
DDRA_BS2#
6
6
DDRA_CLK0
DDRA_CLK0#
6
6
DDRA_CKE0
DDRA_CKE1
6
6
6
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
DDRA_MA14
DDRA_MA15
T7
M7
DDRA_BS0#
DDRA_BS1#
DDRA_BS2#
M2
N8
M3
DDRA_CLK0
DDRA_CLK0#
J7
K7
DDRA_CKE0
DDRA_CKE1
K9
J9
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
J3
K3
L3
DDRA_DQS0
DDRA_DQS#0
F3
G3
DDRA_DQS1
DDRA_DQS#1
C7
B7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
NC5
BA0
BA1
BA2
CK
CK#
CKE
NC2
RAS#
CAS#
WE#
U16
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDRA_DQ5
DDRA_DQ6
DDRA_DQ0
DDRA_DQ7
DDRA_DQ3
DDRA_DQ4
DDRA_DQ1
DDRA_DQ2
DDRA_DQ14
DDRA_DQ9
DDRA_DQ10
DDRA_DQ8
DDRA_DQ11
DDRA_DQ12
DDRA_DQ15
DDRA_DQ13
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VREFCA
VREFDQ
M8
H1
6
6
C
DDRA_CS0#
DDRA_CS1#
DDRA_CS0#
DDRA_CS1#
L2
L1
DDRA_ODT0
K1
J1
DML
DMU
CS#
NC3
Del CS_2(chip select: 1 per Rank)
Del CKE_2(chip select: 1 per Rank???)
RD116 1
RD118 1
5,15
L8
L9
MD@ 2 240_0402_1%
MD@ 2 240_0402_1%
T2
CPU_DRAMRST#
ODT
NC1
ZQ
NC4
RESET#
DDRA_MA14
DDRA_MA15
T7
M7
DDRA_BS0#
DDRA_BS1#
DDRA_BS2#
M2
N8
M3
DDRA_CLK0
DDRA_CLK0#
J7
K7
DDRA_CKE0
DDRA_CKE1
K9
J9
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
J3
K3
L3
DDRA_DQS2
DDRA_DQS#2
F3
G3
DDRA_DQS3
DDRA_DQS#3
C7
B7
1
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
NC5
BA0
BA1
BA2
CK
CK#
CKE
NC2
RAS#
CAS#
WE#
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
B1
B9
D1
D8
E2
E8
F9
G1
G9
2
CD222
0.047U_0402_16V7K2
MD@
DDRA_DQ18
DDRA_DQ21
DDRA_DQ17
DDRA_DQ16
DDRA_DQ22
DDRA_DQ23
DDRA_DQ19
DDRA_DQ20
DDRA_DQ28
DDRA_DQ30
DDRA_DQ29
DDRA_DQ31
DDRA_DQ25
DDRA_DQ26
DDRA_DQ24
DDRA_DQ27
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
DQSL
DQSL#
DQSU
DQSU#
E7
D3
DDRA_CS0#
DDRA_CS1#
L2
L1
DDRA_ODT0
K1
J1
RD95 1 MD@
RD119 1 MD@
2 240_0402_1%
2 240_0402_1%
CPU_DRAMRST#
L8
L9
T2
H5TC4G63AFR-PBA_FBGA96
@
DML
DMU
CS#
NC3
ODT
NC1
ZQ
NC4
RESET#
+0.675VS
Need change to 36ohm 5%
VREFCA
VREFDQ
M8
H1
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
RD122
RD123
RD124
RD125
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_5%
36_0402_5%
36_0402_5%
36_0402_5%
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
RD126
RD127
RD128
RD129
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_5%
36_0402_5%
36_0402_5%
36_0402_5%
DDRA_MA8 RD130
DDRA_MA9 RD131
DDRA_MA10 RD132
DDRA_MA11 RD133
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_5%
36_0402_5%
36_0402_5%
36_0402_5%
DDRA_MA12 RD134
DDRA_MA13 RD135
DDRA_MA14 RD136
DDRA_MA15 RD137
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_5%
36_0402_5%
36_0402_5%
36_0402_5%
DDRA_BS0# RD138
DDRA_BS1# RD139
DDRA_BS2# RD140
DDRA_CKE0 RD141
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_5%
36_0402_5%
36_0402_5%
36_0402_5%
DDRA_CS0# RD142
DDRA_RAS# RD143
DDRA_CAS# RD144
DDRA_WE# RD145
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_5%
36_0402_5%
36_0402_5%
36_0402_5%
DDRA_CKE1 RD146
DDRA_CS1# RD147
1 MD@
1 MD@
2
2
36_0402_5%
36_0402_5%
D
+VREF_CA
+VREF_DQ_DIMMA
1
1
CD223
0.047U_0402_16V7K
@
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
+1.35V
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
+VREF_CA
+VREF_DQ_DIMMA
1
E7
D3
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
+1.35V
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
DQSL
DQSL#
DQSU
DQSU#
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
B1
B9
D1
D8
E2
E8
F9
G1
G9
2
CD225
0.047U_0402_16V7K
@
CD224
0.047U_0402_16V7K2
MD@
+0.675VS
C
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DDRA_CLK0
DDRA_CLK0#
RD63
RD59
1 MD@
1 MD@
2 26.1_0402_1%
2 26.1_0402_1%
DDRA_ODT0
RD117
1 MD@
2 30_0402_1%
+1.35V
H5TC4G63AFR-PBA_FBGA96
@
U17
U18
1
L2
L1
DDRA_ODT0
K1
J1
CS#
NC3
2
1
2
1
DDRA_CS0#
DDRA_CS1#
DML
DMU
ODT
NC1
2
RD8
24.9_0402_1%
BCD@
VREFCA
VREFDQ
RD61 1 MD@
RD120 1 MD@
L8
L9
2 240_0402_1%
2 240_0402_1%
2
CD232
33P_0402_50V8J
CD231
33P_0402_50V8J
2
1
1
2@
2@
MD@
2
1
@2
+1.35V
1
2
1
2@
1
2@
1
2
U18 SIDE
1
CD234
1
MD@
1
2
2
MD@
1
@ 2
MD@
@
2
CD226
0.047U_0402_16V7K2
MD@
CD227
0.047U_0402_16V7K
@
DQSU
DQSU#
VREFCA
VREFDQ
M8
H1
1
2
MD@
1
2
1
1
2@
2@
MD@
@
+VREF_CA
+VREF_DQ_DIMMA
1
1
E7
D3
K1
J1
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
+0.675VS
+1.35V
(10uF_0603_6.3V)*6
1
@
2
1
2
MD@
1
2
MD@
1
2
MD@
1
2
MD@
1
1
2
MD@
2
MD@
@
1
2
@
1
2
1
@2
1
2
10U_0603_6.3V6M
CD179
2
10U_0603_6.3V6M
CD182
1
@
H5TC4G63AFR-PBA_FBGA96
@
1U_0402_6.3V6K
CD183
RESET#
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
1U_0402_6.3V6K
CD180
T2
ZQ
NC4
MD@
1U_0402_6.3V6K
CD178
CPU_DRAMRST#
ODT
NC1
CD229
0.047U_0402_16V7K
@
CD228
0.047U_0402_16V7K2
1U_0402_6.3V6K
CD176
L8
L9
2
10U_0603_6.3V6M
CD177
MD@ 2 240_0402_1%
MD@ 2 240_0402_1%
CS#
NC3
B1
B9
D1
D8
E2
E8
F9
G1
G9
10U_0603_6.3V6M
CD181
H5TC4G63AFR-PBA_FBGA96
@
L2
L1
DDRA_ODT0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
10U_0603_6.3V6M
CD175
RD93 1
RD121 1
DDRA_CS0#
DDRA_CS1#
DML
DMU
For RF
10U_0603_6.3V6M
CD172
RESET#
C7
B7
1
MD@
10U_0603_6.3V6M
CD168
T2
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DDRA_DQS7
DDRA_DQS#7
MD@
1
@
For RF
U17 SIDE
10U_0603_6.3V6M
CD164
CPU_DRAMRST#
ZQ
NC4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
B1
B9
D1
D8
E2
E8
F9
G1
G9
2
B
+1.35V
A1
A8
C1
C9
D2
E9
F1
H2
H9
DQSL
DQSL#
+VREF_DQ_DIMMA
1
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
RAS#
CAS#
WE#
MD@
@
1
1U_0402_6.3V6K
CD221
DQSU
DQSU#
F3
G3
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
MD@
1
@ 2
+VREF_CA
1
E7
D3
J3
K3
L3
DDRA_DQS6
DDRA_DQS#6
CKE
NC2
2
1U_0402_6.3V6K
CD220
C7
B7
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
CK
CK#
2
1U_0402_6.3V6K
CD219
2
DDRA_DQS4
DDRA_DQS#4
+VREF_DQ_DIMMA
MD@
RD7
1.82K_0402_1%
1
CD3
0.022U_0402_16V7-K
BCD@
1
2
2_0402_5%
MD@
K9
J9
1
1U_0402_6.3V6K
CD218
DDR_SA_VREFDQ
M8
H1
J7
K7
DDRA_CKE0
DDRA_CKE1
2
1
1U_0402_6.3V6K
CD217
RD6
6
DQSL
DQSL#
DDRA_CLK0
DDRA_CLK0#
2@
1
1U_0402_6.3V6K
CD216
RD5
1.82K_0402_1%
MD@
RAS#
CAS#
WE#
A1
A8
C1
C9
D2
E9
F1
H2
H9
2@
1
1U_0402_6.3V6K
CD215
F3
G3
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
MD@
1
1U_0402_6.3V6K
CD214
J3
K3
L3
DDRA_DQS5
DDRA_DQS#5
CKE
NC2
MD@
2
1U_0402_6.3V6K
CD213
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
CK
CK#
2
U16 SIDE
1
33P_0402_50V8J
1
2
1
K9
J9
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
1
1U_0402_6.3V6K
CD212
2
J7
K7
DDRA_CKE0
DDRA_CKE1
BA0
BA1
BA2
1U_0402_6.3V6K
CD211
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/ planes
Place near DIMM scoket
+1.35V
DDRA_CLK0
DDRA_CLK0#
15
M2
N8
M3
@2
1U_0402_6.3V6K
CD210
RD12
24.9_0402_1%
BCD@
+VREF_CA
DDRA_BS0#
DDRA_BS1#
DDRA_BS2#
B2
D9
G7
K2
K8
N1
N9
R1
R9
1
CD233
+VREF_CA
2
1
@
0_0402_5%
RD11
1.82K_0402_1%
2
+1.35V
2
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.35V
U15 SIDE
1
33P_0402_50V8J
1
2
1
CD21
0.022U_0402_16V7-K
BCD@
+1.35V
1U_0402_6.3V6K
CD209
RD10
DDR_SM_VREFCA
BA0
BA1
BA2
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
DDRA_DQ52
DDRA_DQ55
DDRA_DQ49
DDRA_DQ51
DDRA_DQ53
DDRA_DQ54
DDRA_DQ48
DDRA_DQ50
DDRA_DQ59
DDRA_DQ60
DDRA_DQ62
DDRA_DQ56
DDRA_DQ63
DDRA_DQ57
DDRA_DQ58
DDRA_DQ61
1U_0402_6.3V6K
CD208
6
B
M2
N8
M3
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
1U_0402_6.3V6K
CD207
Trace width:20 mils
Space:20mils
DDRA_BS0#
DDRA_BS1#
DDRA_BS2#
A14
NC5
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
1U_0402_6.3V6K
CD206
RD9
1.82K_0402_1%
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
1U_0402_6.3V6K
CD205
DDRA_MA14
DDRA_MA15
+1.35V
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
1U_0402_6.3V6K
CD204
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
1U_0402_6.3V6K
CD203
DDRA_DQ47
DDRA_DQ45
DDRA_DQ43
DDRA_DQ40
DDRA_DQ46
DDRA_DQ41
DDRA_DQ42
DDRA_DQ44
DDRA_DQ36
DDRA_DQ39
DDRA_DQ33
DDRA_DQ34
DDRA_DQ37
DDRA_DQ35
DDRA_DQ32
DDRA_DQ38
1U_0402_6.3V6K
CD202
A14
NC5
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
1U_0402_6.3V6K
CD201
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
1U_0402_6.3V6K
CD200
DDRA_MA14
DDRA_MA15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
1U_0402_6.3V6K
CD199
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
1U_0402_6.3V6K
CD198
+1.35V
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
MD@
A
A
Security Classification
Issued Date
Title
LC Future Center Secret Data
2015/02/27
Deciphered Date
2013/08/05
DDR3L MD A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Document Number
4
3
2
Rev
0.2
CG510
Wednesday, May 13, 2015
Date:
5
1
Sheet
14
of
59
5
4
3
2
1
DDR3 SO-DIMM B
DDR_SB_VREFDQ
6
Swap Table
+1.35V
1
+1.35V
RD114
1.82K_0402_1%
D
3A@1.5V
2
RD111
1
2
DDRB_DQ18
DDRB_DQ21
DDRB_DQ3
DDRB_DQ5
1
CD@
DDRB_DQS#0
DDRB_DQS0
RD112
24.9_0402_1%
2
DDRB_DQ6
DDRB_DQ1
DDRB_DQ8
DDRB_DQ10
BCD@
DDRB_DQS#1
DDRB_DQS1
DDRB_DQ14
DDRB_DQ15
DDRB_DQ27
DDRB_DQ26
DDRB_CLK1
DDRB_CLK1#
DDRB_BS1#
DDRB_RAS#
DDRB_CS0#
DDRB_ODT0
DDRB_ODT1
DDRB_CLK1
DDRB_CLK1#
6
DDRB_BS1#
DDRB_RAS#
6
6
DDRB_CS0#
DDRB_ODT0
6
5
DDRB_ODT1
5
6
1
2
1
2
1
2
1
2
1
2
CD@
CD192
1
2
DDRB_DQ35
DDRB_DQ34
1
2
CD193
2.2U_0603_6.3V6K
CD@
2
CD@
1
2
CD@
1
2
CD@
BCD@
+VREF_CA
DDRB_DQ37
DDRB_DQ32
1
1U_0402_6.3V6K
DDRB_MA2
DDRB_MA0
CD63
DDRB_MA6
DDRB_MA4
CD62
2
BCD@
CD@
1
14
CD195
1000P_0402_50V7K
2
DDRB_DQ45
DDRB_DQ41
DDRB_DQS#5
DDRB_DQS5
Layout Note:
Place near DIMM
DDRB_DQ46
DDRB_DQ47
(10U_0603_6.3V)*2
(.1U_0402_10V)*4
DDRB_DQ49
DDRB_DQ53
+0.675VS
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ61
DDRB_DQS#7
DDRB_DQS7
DDRB_DQ58
DDRB_DQ60
1
2
CD@
SMB_DATA_S3
SMB_CLK_S3
SMB_DATA_S3
SMB_CLK_S3
+0.675VS
1
2
1
2
1
2
10U_0603_6.3V6M
RD148
2
1
2
CD67
0_0402_5%
BCD@
1
DDRB_MA11
DDRB_MA7
1U_0402_6.3V6K
1
2
CD43
@
CD@
1
10U_0603_6.3V6M
2
CD42
1
CD61
GND2
BOSS2
2
10U_0603_6.3V6M
GND1
BOSS1
LCN_DAN06-K4406-0103
ME@
1
10U_0603_6.3V6M
CD55
.1U_0402_10V6-K
2
CD66
2
1
.1U_0402_10V6-K
2
205
207
2
CD53
1
1
.1U_0402_10V6-K
CD54
2.2U_0603_6.3V6K
BCD@
A
1
DDRB_MA15
DDRB_MA14
2
CD52
+3VS
2 RD20
@
0_0402_5%
1
2
RD21 10K_0402_5%
@
6
1
.1U_0402_10V6-K
1
DDRB_CKE1
2
CD51
DDRB_DQ59
DDRB_DQ63
DDRB_CKE1
1
.1U_0402_10V6-K
DDRB_DQ62
DDRB_DQ57
DDRB_DQ29
DDRB_DQ25
CD50
DDRB_DQ50
DDRB_DQ48
+1.35V
DDRB_DQS#3
DDRB_DQS3
CD41
DDRB_DQS#6
DDRB_DQS6
DDRB_DQ31
DDRB_DQ30
1U_0402_6.3V6K
DDRB_DQ52
DDRB_DQ51
DDRB_DQ9
DDRB_DQ11
CD60
DDRB_DQ42
DDRB_DQ44
6
6
(10uF_0603_6.3V)*8
(1U_0402_6.3V)*8
(.1U_0402_10V6-K)*4
Layout Note:
Place near DIMM
10U_0603_6.3V6M
DDRB_DQ40
DDRB_DQ43
CD230
0.1U_0402_25V6
2 EMC_NS@
CD40
DDRB_DQ39
DDRB_DQ38
B
6
5,14
1U_0402_6.3V6K
DDRB_DQS#4
DDRB_DQS4
DDRB_DQ13
DDRB_DQ12
.1U_0402_10V6-K
DDRB_DQ33
DDRB_DQ36
1
CD47
DDRB_MA13
DDRB_CS1#
CPU_DRAMRST#
DDRB_DQ0
DDRB_DQ7
10U_0603_6.3V6M
DDRB_CS1#
CPU_DRAMRST#
CD39
DDRB_W E#
DDRB_CAS#
6
2
.1U_0402_10V6-K
6
6
DDRB_W E#
DDRB_CAS#
DDRB_DQS[0..7]
DDRB_DQ2
DDRB_DQ4
CD46
DDRB_BS0#
1
.1U_0402_10V6-K
6
DDRB_MA10
DDRB_BS0#
@
CD45
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK0
DDRB_CLK0#
2
.1U_0402_10V6-K
6
6
1
.1U_0402_10V6-K
DDRB_MA3
DDRB_MA1
@
CD44
DDRB_MA8
DDRB_MA5
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
2
10U_0603_6.3V6M
DDRB_MA12
DDRB_MA9
CKE1
VDD_2
A15
A14
VDD_4
A11
A7
VDD_6
A6
A4
VDD_8
A2
A0
VDD_10
CK1
CK1#
VDD_12
BA1
RAS#
VDD_14
S0#
ODT0
VDD_16
ODT1
NC_2
VDD_18
VREF_CA
VSS_28
DQ36
DQ37
VSS_30
DM4
VSS_32
DQ38
DQ39
VSS_34
DQ44
DQ45
VSS_35
DQS5#
DQS5
VSS_38
DQ46
DQ47
VSS_40
DQ52
DQ53
VSS_42
DM6
VSS_44
DQ54
DQ55
VSS_46
DQ60
DQ61
VSS_48
DQS7#
DQS7
VSS_50
DQ62
DQ63
VSS_52
EVENT#
SDA
SCL
VTT_2
1
CD38
DDRB_BS2#
CKE0
VDD_1
NC_1
BA2
VDD_3
A12/BC#
A9
VDD_5
A8
A5
VDD_7
A3
A1
VDD_9
CK0
CK0#
VDD_11
A10/AP
BA0
VDD_13
WE#
CAS#
VDD_15
A13
S1#
VDD_17
TEST
VSS_27
DQ32
DQ33
VSS_29
DQS4#
DQS4
VSS_31
DQ34
DQ35
VSS_33
DQ40
DQ41
VSS_36
DM5
VSS_37
DQ42
DQ43
VSS_39
DQ48
DQ49
VSS_41
DQS6#
DQS6
VSS_43
DQ50
DQ51
VSS_45
DQ56
DQ57
VSS_47
DM7
VSS_49
DQ58
DQ59
VSS_51
SA0
VDDSPD
SA1
VTT_1
@
DDRB_DQ19
DDRB_DQ20
10U_0603_6.3V6M
DDRB_BS2#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDRB_DQS#2
DDRB_DQS2
CD37
6
DDRB_CKE0
6
DDRB_MA[0..15]
10U_0603_6.3V6M
DDRB_CKE0
DDRB_DQ[0..63]
DDRB_DQS#[0..7]
DDRB_DQ16
DDRB_DQ22
10U_0603_6.3V6M
6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CD36
DDRB_DQ28
DDRB_DQ24
C
VSS_2
DQ4
DQ5
VSS_4
DQS0#
DQS0
VSS_6
DQ6
DQ7
VSS_8
DQ12
DQ13
VSS_10
DM1
RESET#
VSS_12
DQ14
DQ15
VSS_14
DQ20
DQ21
VSS_16
DM2
VSS_18
DQ22
DQ23
VSS_20
DQ28
DQ29
VSS_22
DQS3#
DQS3
VSS_24
DQ30
DQ31
VSS_26
CD35
33P_0402_50V8J
DDRB_DQ17
DDRB_DQ23
VREF_DQ
VSS_1
DQ0
DQ1
VSS_3
DM0
VSS_5
DQ2
DQ3
VSS_7
DQ8
DQ9
VSS_9
DQS1#
DQS1
VSS_11
DQ10
DQ11
VSS_13
DQ16
DQ17
VSS_15
DQS2#
DQS2
VSS_17
DQ18
DQ19
VSS_19
DQ24
DQ25
VSS_21
DM3
VSS_23
DQ26
DQ27
VSS_25
CD34
33P_0402_50V8J
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CD33
33P_0402_50V8J
1
.1U_0402_10V6-K
2
CD31
1
2.2U_0603_6.3V6K
2
RD115
1.82K_0402_1%
BCD@
CD191
0.022U_0402_16V7-K
1
For RF
JDDR1
+VREF_DQ_DIMMB
CD194
1
2
2_0402_5%
Pin
Number
+1.35V
1
2
CD@
Pin Name
Net Name
5
7
15
17
4
6
16
18
10
12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS#0
DQS0
DDRB_DQ17
DDRB_DQ23
DDRB_DQ18
DDRB_DQ21
DDRB_DQ16
DDRB_DQ22
DDRB_DQ19
DDRB_DQ20
DDRB_DQS#2
DDRB_DQS2
21
23
33
35
22
24
34
36
27
29
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS#1
DQS1
DDRB_DQ3
DDRB_DQ5
DDRB_DQ6
DDRB_DQ1
DDRB_DQ2
DDRB_DQ4
DDRB_DQ0
DDRB_DQ7
DDRB_DQS#0
DDRB_DQS0
39
41
51
53
40
42
50
52
45
47
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS#2
DQS2
DDRB_DQ8
DDRB_DQ10
DDRB_DQ14
DDRB_DQ15
DDRB_DQ13
DDRB_DQ12
DDRB_DQ9
DDRB_DQ11
DDRB_DQS#1
DDRB_DQS1
57
59
67
69
56
58
68
70
62
64
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS#3
DQS3
DDRB_DQ27
DDRB_DQ26
DDRB_DQ28
DDRB_DQ24
DDRB_DQ31
DDRB_DQ30
DDRB_DQ29
DDRB_DQ25
DDRB_DQS#3
DDRB_DQS3
129
131
141
143
130
132
140
142
135
137
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS#4
DQS4
DDRB_DQ33
DDRB_DQ36
DDRB_DQ39
DDRB_DQ38
DDRB_DQ37
DDRB_DQ32
DDRB_DQ35
DDRB_DQ34
DDRB_DQS#4
DDRB_DQS4
147
149
157
159
146
148
158
160
152
154
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS#5
DQS5
DDRB_DQ40
DDRB_DQ43
DDRB_DQ42
DDRB_DQ44
DDRB_DQ45
DDRB_DQ41
DDRB_DQ46
DDRB_DQ47
DDRB_DQS#5
DDRB_DQS5
163
165
175
177
164
166
174
176
169
171
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS#6
DQS6
DDRB_DQ52
DDRB_DQ51
DDRB_DQ50
DDRB_DQ48
DDRB_DQ49
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQS#6
DDRB_DQS6
181
183
191
193
180
182
192
194
186
188
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS#7
DQS7
DDRB_DQ62
DDRB_DQ57
DDRB_DQ59
DDRB_DQ63
DDRB_DQ56
DDRB_DQ61
DDRB_DQ58
DDRB_DQ60
DDRB_DQS#7
DDRB_DQS7
D
C
B
CD@
7,40
7,40
0.65A@0.75V
206
208
1
2
CD69
33P_0402_50V8J
@
A
For RF
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
DDR3L SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
2
Sheet
1
15
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Security Classification
Issued Date
Title
LC Future Center Secret Data
2015/02/27
Deciphered Date
Blank
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Document Number
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Date:
5
1
Sheet
16
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Blank
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
17
of
59
5
4
3
2
1
N15x GPIO
GPIO
I/O
GPIO0
OUT
GPIO1
D
OUT
ACTIVE
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
Function Description
N/A
OUT
N/A
GPIO3
OUT
N/A
GPIO4
OUT
N/A
GPIO5
OUT
N/A
GPU power sequencing---3V3_MAIN_EN
GPIO6
IN
-
GPU wake signal for GC6 2.0
GPIO7
OUT
N/A
GPIO8
I/O
-
System side PCIe reset Monitor
GPIO9
I/O
N/A
2.2K Pull-up
GPIO10
OUT
N/A
GPIO11
OUT
-
GPU Core VDD PWM control signal
GPIO12
IN
GPIO13
OUT
-
Phase Shedding
GPIO15
IN
N/A
GPIO16
IN
N/A
GPIO18
IN
N/A
GPIO19
IN
N/A
GPIO20
(V)
(A)
(W)
(A)
(W)
(A)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
N14X
128bit
2GB
DDR3
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NVVDD
Logical
Strapping Bit3
Logical
Strapping Bit2
Logical
Strapping Bit1
Logical
Strapping Bit0
+3VGS
SOR3_EXPOSED
SOR2_EXPOSED
SOR1_EXPOSED
SOR0_EXPOSED
ROM_SI
+3VGS
RAM_CFG[3]
RAM_CFG[2]
RAM_CFG[1]
RAM_CFG[0]
ROM_SO
+3VGS
DEVID_SEL
PCIE_CFG
SMB_ALT_ADDR
VGA_DEVICE
STRAP0
+3VGS
STRAP1
+3VGS
STRAP2
+3VGS
STRAP3
+3VGS
STRAP4
+3VGS
Physical
Strapping pin
ROM_SCLK
N/A
GPIO17
(MHz)
(3.3V)
(10K pull High)
C
N/A
Other
NVCLK
/MCLK
(W)
N15x Multi-level Straps
AC Power Detect Input
IN
I/O and
PLLVDD
(1.05V)
Mem
(1,5)
(W)
D
GPIO2
GPIO14
FBVDD
(1.35V)
FBVDDQ
PCI Express
(GPU+Mem) (1.05V)
(1.35V)
(6)
GPU
(4)
Products
FB Enable for GC6 2.0
N/A
Power Rail
C
Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
Reserved(keep pull-up and pull-down footprint and not stuff by default)
SMBUS_ALT_ADDR
GPIO21
OUT
GPU PCIe self-reset control
0
0x9E (Default)
OVERT
OUT
Active Low Thermal Catastrophic Over Temperature
1
0x9C (Multi-GPU usage)
N15V-GM Power Sequence
N15x Binary Straps
B
+3VG_AON
Other Power rail
B
+VGA_CORE
+3VG_AON
tNVVDD >0
+1.35VGS
Tpower-off <10ms
tFBVDDQ >0
+1.05VS_VGA
tPEX_VDD >0
1. all power rail ramp up time should be larger than 40us
1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
Physical
Strapping pin
ROM_SCLK
Power Rail
Strap Mapping
+3VGS
SMB_ALT_ADDR
ROM_SI
+3VGS
SUB_VENDOR
ROM_SO
+3VGS
VGA_DEVICE
STRAP0
+3VGS
RAM_CFG[0]
STRAP1
+3VGS
RAM_CFG[1]
STRAP2
+3VGS
RAM_CFG[2]
STRAP3
+3VGS
RAM_CFG[3]
STRAP4
+3VGS
PCIE_MAX_SPEED
N15S-GT Power Sequence
+3VG_AON
+VGA_CORE
A
A
tNVVDD >0
+1.05VS_VGA
+1.35VGS
tPEX_VDD >0
Issued Date
Title
LC Future Center Secret Data
Security Classification
1. all power rail ramp up time should be larger than 40us
2015/02/27
Deciphered Date
2014/01/21
VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
18
of
60
5
4
9
3
2
1
PCIE_CRX_GTX_N[0..3]
9
PCIE_CRX_GTX_P[0..3]
9
PCIE_CTX_C_GRX_N[0..3]
9
PCIE_CTX_C_GRX_P[0..3]
UV1A
Part 1 of 6
1
CV11
.1U_0402_10V6-K
@
5
2
VCC
UV2
IN2
OUT
PLT_RST_VGA#
4
MC74VHC1G08DFT2G_SC70-5
@
RV14
10K_0402_5%
@
1
2
2
IN1
3
PLT_RST#
1
GND
PXS_RST#
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
AC9
AB9
AB10
AC10
AD11
AC11
AC12
AB12
AB13
AC13
AD14
AC14
AC15
AB15
AB16
AC16
AD17
AC17
AC18
AB18
AB19
AC19
AD20
AC20
AC21
AB21
AD23
AE23
AF24
AE24
AG24
AG25
+3VGS
2
8,32,37,40,44
1
PLT_RST#
8
Differential signal
1
2
PXS_RST#
PLT_RST#
NC100
NC101
CLK_PCIE_GPU
CLK_PCIE_GPU#
CLK_REQ_GPU#
CLK_PCIE_GPU
CLK_PCIE_GPU#
AE8
AD8
AC6
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
PEX_TSTCLK_OUT
2 RV32
200_0402_1% PEX_TSTCLK_OUT#
AF22
AE22
PLT_RST_VGA#
PEX_TERMP
1
2 RV35
OPT@ 2.49K_0402_1%
AC7
AF25
1
@
BAT54AWT1G_SOT323-3
OPT@
OVERT#
W5
AE2
AF2
CV221
0.01U_0402_25V7K
@
3
1
1
2
CV218
@
WRST#
44
QV23
2N7002KW_SOT323-3
OPT@
2
C
B7
A7
C9
C8
A9
B9
D9
D8
VGA_SMB_CK2
VGA_SMB_DA2
+3VG_AON
Internal Thermal Sensor
60mA
CORE_PLLVDD
SP_PLLVDD
L6
M6
N6
OVERT#
RV20 1
VGA_ALERT#
RV23 1
+PLLVDD
45mA
1
45mA
+SP_PLLVDD
2 RV24
OPT@
0_0402_5%
VGA_AC_DET_R
+3VG_AON
PSI_VGA
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
PEX_TSTCLK
PEX_TSTCLK_N
PLT_RST_VGA#
3
AE3
AE4
1
NC102
NC103
NC104
VID_PLLVDD
8
RV180
2.2K_0402_5%
OPT@
DV2
4
B
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
NC89
NC90
NC91
NC92
NC93
NC94
NC95
NC96
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
2 0_0402_5%
OPT@
PEX_RST_N
PEX_TERMP
RV33 1
XTALOUT
XTAL_IN
XTAL_OUT
XTAL_SSIN
XTAL_OUTBUFF
XTAL_IN
XTAL_OUT
C11
B10
2
OPT@ 10K_0402_5%
2
OPT@ 10K_0402_5%
RV26 1
2
OPT@ 100K_0402_5%
RV29 1
2
OPT@ 10K_0402_5%
2
10K_0402_5%
@
B
A10 XTALSSIN
C10 XTALOUT
1
1
OPT@ 2 RV21
OPT@ 2 RV22
10K_0402_5%
10K_0402_5%
300ohms (ESR=0.2) Bead
Under GPU(below 150mils)
1
OPT@
1
+SP_PLLVDD
N16V-GM-S-B1_FCBGA595
OPT@
150mA
1
1
CV15
2
OPT@
1
CV16
2
OPT@
1
2
@
CV17
22U_0805_6.3V6M
C
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
44
58
10U_0603_6.3V6M
2 0_0402_5%
2
2
2
2
2
2
2
2
1 RV174
AG3
AF4
AF3
D
RV12 1
OPT@ 1
OPT@ 1
OPT@ 1
OPT@ 1
OPT@ 1
OPT@ 1
OPT@ 1
OPT@ 1
PSI_VGA
OVERT#
PLT_RST_VGA#
NC97
NC98
NC99
VGA_AC_DET
PSI_VGA
2 RV6
0_0402_5%
1
N15SGT@
A6
AB6
DV1
58
2
1
@
RB751V-40_SOD323-2
NVVDD PWM_VID
S
+3VGARST
CV10
CV13
CV8
CV9
CV6
CV7
CV4
CV5
NVVDD PWM_VID
VGA_AC_DET_R
PSI_VGA_R
G
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
+3VG_AON
OVERT
NC33
A6 Symbol update to OVER
VGA_ALERT#
0.1U_0402_10V7K
PU AT EC SIDE, +3VS AND 4.7K
D
0.1U_0402_10V7K
0_0402_5% VGA_SMB_DA2
C6
B2
D6
C7
F9
A3
A4
B6
E9
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4
.1U_0402_10V6-K
0_0402_5% VGA_SMB_CK2
2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
2
2
1OPT@
GPIO
1OPT@
RV9
DACs
EC_SMB_DA2
RV7
PCI EXPRESS
7,44
EC_SMB_CK2
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
NC81
NC82
NC83
NC84
NC85
NC86
NC87
NC88
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
CLK
7,44
AG6
AG7
AF7
AE7
AE9
AF9
AG9
AG10
AF10
AE10
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
I2C
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
D
1
2
2
CV19
OPT@
2
OPT@
30ohms (ESR=0.05) Bead
OSC1
GND2
GND1
OSC2
Under GPU
4
1
OPT@
1
Near GPU
+PLLVDD
3
27MHZ_10PF_7V27000050
OPT@
2 RV176
0_0402_5%
2 LV2
+1.05VGS
XTAL_OUT
10P_0402_50V8J
10P_0402_50V8J
1
+1.05VGS
PBY160808T-301Y-N_2P
@
CV18
2 RV38
OPT@ 10M_0402_5%
YV1
XTAL_IN
1
2 RV175
0_0402_5%
2 LV1
1
1
CV20
OPT@
CV21
0.1U_0402_10V7K
2
OPT@
2
PBY160808T-300Y-N_2P
@
1
2
CV22
22U_0805_6.3V6M
OPT@
A
A
8
1
GPU_CLKREQ#
2 RV48
OPT@
0_0402_5%
CLK_REQ_GPU#
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
2014/01/21
N16X_PCIE/ DAC/ GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
5
4
3
2
1
Sheet
19
of
60
5
4
3
2
1
D
D
UV1C
Part 3 of 6
AB5
AB4
AB3
AB2
AD3
AD2
AE1
AD1
AD4
AD5
NC105
NC106
NC107
NC108
NC109
NC110
NC111
NC112
NC113
NC114
FERMI_RSVD1
FERMI_RSVD2
NC56
NC57
NC58
NC59
NC60
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC
AC3
AC4
Y4
Y3
AA3
AA2
AB1
AA1
AA4
AA5
NC50
NC51
NC52
NC115
NC116
NC117
NC118
NC119
NC120
NC121
NC122
NC123
NC124
C
V3
V4
U3
U4
T4
T5
R4
R5
N1
M1
M2
M3
K2
K3
K1
J1
M4
M5
L3
L4
K4
K5
J4
J5
N4
N5
B
P3
P4
J2
J3
H3
H4
NC133
NC134
NC135
NC136
NC137
NC138
NC139
NC140
PGOOD
GENERAL
NC125
NC126
NC127
NC128
NC129
NC130
NC131
NC132
LVDS/TMDS
BUFRST_N
T2
T3
T1
R1
R2
R3
N2
N3
NC71
NC72
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
NC73
MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GNDMLS_REF1
MULTI_STRAP_REF2_GND
F11
AD10
AD7
V5
V6
G1
G2
G3
G4
G5
G6
G7
V1
V2
W1
W2
W3
W4
2
D11
@
1 RV50
10K_0402_5%
D10
E10
F10
D1
D2
E4
E3
D3
C1
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
1
OPT@
F6
F4
F5
2
28
28
28
28
28
C
2 RV51
40.2K_0402_1%
RV11
1
+3VG_AON
@ 10K_0402_5%
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
THERMDP
THERMDN
NC42
NC43
NC44
NC45
NC46
VDD_SENSE
F12
E12
F2
VCCSENSE_VGA
VCCSENSE_VGA
58
trace width: 16mils
differential voltage sensing.
differential signal routing.
NC47
NC48
GND_SENSE
NC49
NC141
NC142
F1
VSSSENSE_VGA
AD9
AE5
AE6
AF6
AD6
AG4
TESTMODE
@
@
@
@
VSSSENSE_VGA
58
TEST
NC143
NC144
NC145
NC146
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
NC147
NC148
SERIAL
TV1
TV2
TV3
1TV4
OPT@
D12
B12
A12
C12
@ 1
ROM_SI
ROM_SO
ROM_SCLK
C
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK
1 OPT@
1
1
1
1
2 RV52
10K_0402_5%
B
2 RV53
10K_0402_5%
TV5
ROM_SI
ROM_SO
ROM_SCLK
28
28
28
N16V-GM-S-B1_FCBGA595
OPT@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
2014/01/21
N16X_LVDS/ HDMI/ THERM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
20
of
60
3
2
3
1
CV215
33P_0402_50V8J
CV49
CV48
4.7U_0603_6.3V6K
1U_0402_6.3V6K
2
OPT@
2
OPT@
Place near balls(Under GPU)
Place near GPU
+3VGS
1
OPT@
2 RV55
40.2_0402_1%
OPT@
2 RV56
42.2_0402_1%
OPT@
2 RV57
51.1_0402_1%
1
B25 FB_CAL_TERM 1
2
@
2
OPT@
2
OPT@
1
CV53
1
CV52
CV51
1
4.7U_0603_6.3V6K
C24 FB_CAL_GND
1
1U_0402_6.3V6K
D22 FB_CAL_VDDQ 1
CV50
+1.35VGS
.1U_0402_10V6-K
+VDD33
2
0_0603_5%
Change RV9 to 0ohm jump
2
OPT@
CALIBRATION PIN
DDR3
FB_CAL_x_PD_VDDQ
40.2Ohm
FB_CAL_x_PU_GND
42.2Ohm
FB_CAL_xTERM_GND
51.1Ohm
C
+3VG_AON
Under GPU(below 150mils)
AA8
AA9
AB8
120mA
NC76
NC77
NC78
NC79
NC80
PEX_PLLVDD_1
PEX_PLLVDD_2
AA14
AA15
1
2
OPT@
1
2
OPT@
1
2
@
+1.05VGS
RV62
+PEX_PLLVDD
1
S
N16V-GM-S-B1_FCBGA595
OPT@
1
2
OPT@
1
2
OPT@
1
2 0_0603_5%
CV60
PEX_PLL_HVDD_1
PEX_PLL_HVDD_2
QV10
2N7002KW _SOT323-3
@
S
CV39
10U_0603_6.3V6M
CV37
4.7U_0603_6.3V6K
CV33
.1U_0402_10V6-K
2
OPT@
1
CV59
D
2
G
+3VG_AON
Near
1
4.7U_0805_25V6-K
3
2
1.05VGS_EN#
QV9
2N7002KW _SOT323-3
G
For RF
Place near balls
PEX_SVDD_3V3
J7
K7
K6
H6
J6
2
@
RV54
3V3_MAIN_1
3V3_MAIN_2
FB_CAL_TERM
RV59
470_0603_5%
@
QV8
S 2N7002KW _SOT323-3
D
2
OPT@
RV61
120K_0402_5%
OPT@
NC158
NC159
NC160
NC161
Under
CV58
1
CV54
0.1U_0402_16V4Z
OPT@
1
1
1.05VGS_EN
3
EN_VGA
2
2
G
OPT@
22,58
D
2
1
1
1.05VGS_EN#
2
RV60
47K_0402_5%
T7
R7
U6
R6
2
@
G10
G12
G8
G9
@
1
OPT@2 RV58
100K_0402_5%
1 OPT@
AA22
AB23
AC24
AD25
AE26
AE27
1U_0402_6.3V6K
CV220
0.1U_0402_16V4Z
@
1
D
.1U_0402_10V6-K
+5VALW
2
NC154
NC155
NC156
NC157
1
B+
4
C
M7
N7
T6
P6
1
OPT@
CV57
5
1
3V3_AON_1
3V3_AON_2
FB_CAL_GND
1
2
3
OPT@
2
+3VG_AON
FB_CAL_VDDQ
QV7
AON6414AL_DFN8-5
2
.1U_0402_10V6-K
NC150
NC151
NC152
NC153
1
+1.05VGS
1
CV56
W7
AA6
W6
Y6
4
OPT@
Reserve for GPU +1.05V
NC149
2
OPT@
CV55
S1
S2
S3
D
V7
G
5
+1.05VGS
1
2
3
FBVDDQ_AON_1
FBVDDQ_AON_2
FBVDDQ_AON_3
FBVDDQ_AON_4
1
4.7U_0603_6.3V6K
QV24
AON7408L_DFN8-5
+1.05VS
H24
H26
J21
K21
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6
+1.05VGS
Under GPU(below 150mils)
AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27
.1U_0402_10V6-K
D
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
1U_0402_6.3V6K
2
OPT@
FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
CV43
CV32
CV31
2
OPT@
1
Near GPU
2000mA
Part 4 of 6
B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
L22
L24
L26
M21
N21
R21
T21
V21
W21
POWER
2
OPT@
1
0.1U_0402_10V7K
2
OPT@
1
CV30
CV29
1
3.5A
0.1U_0402_10V7K
2
@
1U_0402_6.3V6K
CV28
CV27
2
OPT@
1
1U_0402_6.3V6K
1
OPT@
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
OPT@
2
Under GPU(below 150mils)
CV26
CV25
1
10U_0603_6.3V6M
22U_0805_6.3V6M
Near GPU
1
CV47
UV1D
+1.35VGS
4.7U_0603_6.3V6K
4
22U_0805_6.3V6M
5
2
OPT@
Place near balls
B
B
+1.35V
+1.35V TO +1.35VGS
D
D
OPT@
QV13
PXS_PW REN#
2
1
CV70
1
RV67
470_0603_5%
@
2
2
1
1
2
CV69
.1U_0402_10V6-K
OPT@
4
1
RV69
1
2
FBVDDQ_PW R_EN#
QV15
2N7002KW _SOT323-3
@
G
2
47K_0402_5%
OPT@
D
D
2
S
D
1
3
2
FBVDDQ_PW R_EN#
1
OPT@2 RV68
100K_0402_5%
CV63
10U_0603_6.3V6M
OPT@
CV71
0.01U_0402_25V7K
QV17A
OPT@
2N7002KDW H_SOT363-6
2
OPT@
S
RV70
124K_0402_1%
OPT@
1
1
OPT@
CV64
.1U_0402_10V6-K
2
CV68
1
RV64
470_0603_5%
@
G
2
+
2
2
CV62
0.01U_0402_25V7K
@
1
2
G
D
@
3
G
3
2
CV67
1
+5VALW
1
2
LP2301ALT1G_SOT23-3
2
1
OPT@
3
2
2 RV65
10K_0402_5%
OPT@
QV14
B+
1
2
1
2
PXS_PW REN
1
1
QV12
4,58
1
OPT@
G
@
CV61
.1U_0402_10V6-K
1
2
6
S
3
QV11
OPT@
CV66
1
10U_0603_6.3V6M
@
+5VALW
CV65
1
10U_0603_6.3V6M
OPT@
+3VG_AON
10U_0603_6.3V6M
OPT@
10U_0603_6.3V6M
OPT@
5
+3VS
PXS_PW REN#
1
2
3
220U_B2_2.5VM_R15M
@
+3.3VS TO +3VG_AON
RV63
47K_0402_5%
+1.35VGS
AON6414AL_DFN8-5
58
S 2N7002KW _SOT323-3
5
DGPU_PW ROK
G
S 2N7002KW _SOT323-3
QV17B
2N7002KDW H_SOT363-6
OPT@
4
S
A
A
+3VGS
+3VG_AON
+3.3VS TO +3VGS
2
Issued Date
OPT@
Title
LC Future Center Secret Data
Security Classification
RV171 1
0_0603_5%
2015/02/27
Deciphered Date
2014/01/21
N16X_Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
21
of
60
5
4
3
2
1
D
D
UV1E
UV1F
GND_113
GND_114
+VGA_CORE
K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5
+VGA_CORE
K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
+VGA_CORE
2
OPT@
2
OPT@
1
2
@
OPT@
OPT@
OPT@
OPT@
OPT@
2
@
2
@
1
CV88
1
CV87
1
4.7U_0603_6.3V6K
2
CV86
1
4.7U_0603_6.3V6K
2
CV85
1
4.7U_0603_6.3V6K
2
CV84
CV83
1
4.7U_0603_6.3V6K
2
4.7U_0603_6.3V6K
CV82
1
4.7U_0603_6.3V6K
CV81
4.7U_0603_6.3V6K
CV80
4.7U_0603_6.3V6K
2
2
@
CV213
33P_0402_50V8J
VDD_041
VDD_040
VDD_039
VDD_038
VDD_037
VDD_036
VDD_035
VDD_034
VDD_033
VDD_032
VDD_031
VDD_030
VDD_029
VDD_028
VDD_027
VDD_026
VDD_025
VDD_024
VDD_023
VDD_022
VDD_021
2
@
2
2
@
N16V-GM-S-B1_FCBGA595
OPT@
1
CV102
CV101
CV100
@
1
4.7U_0603_6.3V6K
2
@
1
4.7U_0603_6.3V6K
2
@
1
CV99
CV98
1
4.7U_0603_6.3V6K
2
@
C
4.7U_0603_6.3V6K
2
OPT@
1
1
For RF
1
CV97
CV96
4.7U_0603_6.3V6K
2
OPT@
1
2
OPT@
CV92
1
1
4.7U_0603_6.3V6K
CV79
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CV78
2
@
1U_0402_6.3V6K
CV91
CV95
1
2
VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020
V18
V16
V14
V12
V10
U17
U15
U13
U11
T18
T16
T14
T12
T10
R17
R15
R13
R11
P18
P16
P14
2
@
For RF
1
CV214
CV104
1
2
OPT@
1
OPT@
4.7U_0603_6.3V6K
CV77
4.7U_0603_6.3V6K
1U_0402_6.3V6K
CV90
2
1
CV105
1
OPT@
22U_0805_6.3V6M
1
2
OPT@
2
33P_0402_50V8J
2
@
1
1
OPT@
22U_0805_6.3V6M
1
1U_0402_6.3V6K
2
OPT@
2
OPT@
4.7U_0603_6.3V6K
CV89
1
CV93
1U_0402_6.3V6K
OPT@
1
CV94
2
4.7U_0603_6.3V6K
CV76
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
Under GPU
POWER
Part 6 of 6
4.7U_0603_6.3V6K
GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
CV103
Part 5 of 6
22U_0805_6.3V6M
C
GND_001
GND_002
GND_003
GND_004
GND_005
GND_006
GND_007
GND_008
GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016
GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037
GND_038
GND_039
GND_040
GND_041
GND_042
GND_043
GND_044
GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056
GND
A2
A26
AB11
AB14
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5
2
@
Near GPU
AA7
AB7
N16V-GM-S-B1_FCBGA595
OPT@
B
B
+VGA_CORE
1
+5VALW
2
RV173
470_0603_5%
@
EN_VGA
QV21
@
1 2
2
G
D
QV22
D
G
3
21,58
2
@
3
1
1
RV172
47K_0402_5%
@
S
2N7002KW _SOT323-3
S
2N7002KW _SOT323-3
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
2014/01/21
N16X_+VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
22
of
60
5
4
3
2
1
FBA_D[0..63]
24,25
24,25
24,25
24,25
FBA_D[0..63]
FBA_DQM[7..0]
FBA_DQS[7..0]
FBA_DQS#[7..0]
CMD mapping mod Mode D
Rank0
Address
UV1B
FBx_CMD0
D
C
30ohms (ESR=0.01) Bead
+1.05VGS
+FB_PLLAVDD
200mA
1
2 LV4
HCB1608KF-300T60_2P
OPT@
Place close to BGA
2
OPT@
1
CV113
CV112
1
0.1U_0402_10V7K
2
OPT@
Place close to ball
1U_0402_6.3V6K
1
CV111
+FB_PLLAVDD
22U_0805_6.3V6M
Place close to BGA
2
OPT@
E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25
F16
P22
D23
+FB_PLLAVDD
FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_CMD00
FBA_CMD01
FBA_CMD02
FBA_CMD03
FBA_CMD04
FBA_CMD05
FBA_CMD06
FBA_CMD07
FBA_CMD08
FBA_CMD09
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32
MEMORY
INTERFACE A
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FB_PLLAVDD_1
FB_PLLAVDD_2
FB_VREF
Place close to ball
1
2
OPT@
1
RV120 OPT@
H22
CV115
0.1U_0402_10V7K
FB_CLAMP F3
2
10K_0402_5%
FB_DLLAVDD
FB_CLAMP
32..63
CS0#
D
FBx_CMD1
Part 2 of 6
B
0..31
FBA_CMD34
FBA_CMD35
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26
B19
FBA_CS0#
FBA_ODT0
FBA_CKE0
FBA_A14
FBA_RST#
FBA_A9
FBA_A7
FBA_A2
FBA_A0
FBA_A4
FBA_A1
FBA_BA0
FBA_W E
FBA_CAS#
FBA_CS1#
FBA_ODT1
FBA_CKE1
FBA_A13
FBA_A8
FBA_A6
FBA_A11
FBA_A5
FBA_A3
FBA_BA2
FBA_BA1
FBA_A12
FBA_A10
FBA_RAS#
FBA_CS0#
24
FBA_ODT0
FBA_CKE0
FBA_A14
FBA_RST#
FBA_A9
FBA_A7
FBA_A2
FBA_A0
FBA_A4
FBA_A1
FBA_BA0
FBA_W E
24
24
24,25
24,25
24,25
24,25
24,25
24,25
24,25
24,25
24,25
24,25
FBA_CAS#
FBA_CS1#
24,25
25
FBA_ODT1
25
FBA_CKE1
25
FBA_A13
24,25
FBA_A8
24,25
FBA_A6
24,25
FBA_A11
24,25
FBA_A5
24,25
FBA_A3
24,25
FBA_BA2
24,25
FBA_BA1
24,25
FBA_A12
24,25
FBA_A10
24,25
FBA_RAS#
24,25
+1.35VGS
2
2
@
D19
D14
C17
C22
P24
W24
AA25
U25
@
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
F19
C14
A16
A22
P25
W22
AB27
T27
FBA_DQS#0
FBA_DQS#1
FBA_DQS#2
FBA_DQS#3
FBA_DQS#4
FBA_DQS#5
FBA_DQS#6
FBA_DQS#7
E19
C15
B16
B22
R25
W23
AB26
T26
FBA_DQS0
FBA_DQS1
FBA_DQS2
FBA_DQS3
FBA_DQS4
FBA_DQS5
FBA_DQS6
FBA_DQS7
D24
D25
FBA_CLK0
FBA_CLK0#
N22
M22
FBA_CLK1
FBA_CLK1#
ODT0
FBx_CMD3
CKE0
FBx_CMD4
A14
A14
FBx_CMD5
RST
RST
FBx_CMD6
A9
A9
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE
WE
FBx_CMD14
A15
A15
FBx_CMD15
CAS#
CAS#
CS1#
FBx_CMD16
FBx_CMD17
ODT1
FBx_CMD18
Symbol update to FBA_CMD34/35
F22 RV121
J22 RV122
FBx_CMD2
C
CKE1
FBx_CMD19
1 60.4_0402_1%
1 60.4_0402_1%
FBx_CMD20
A13
A13
FBx_CMD21
A8
A8
FBx_CMD22
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
FBx_CMD30
RAS#
RAS#
FBx_CMD31
FBx_CMD32
FBx_CMD33
FBA_CLK0
FBA_CLK0#
24
24
FBA_CLK1
FBA_CLK1#
25
25
FBx_CMD34
DBG0
FBx_CMD35
DBG1
D18
C18
D17
D16
T24
U24
V24
V25
B
N16V-GM-S-B1_FCBGA595
OPT@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
N16X_MEM Interface
2014/01/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
23
of
60
5
4
3
2
1
at least 16 mils width(optimal)
20 mils spacing to other signals /planes
FBA_D[0..63]
23,25
D
D
+1.35VGS
FBA_DQM[7..0]
1
2
RPV6
UV6
4
3
+FBA_VREFCA0
1.33K_0404_4P2R_1%
RANKA@
1
2
+FBA_VREFCA0
+FBA_VREFDQ0
CV116
.01U_0402_16V7-K
RANKA@
23,25
23,25
23,25
23,25
23,25
23,25
23,25
23,25
23,25
23,25
23,25
23,25
23,25
23,25
23,25
+1.35VGS
FBA_A0
FBA_A1
FBA_A2
FBA_A3
FBA_A4
FBA_A5
FBA_A6
FBA_A7
FBA_A8
FBA_A9
FBA_A10
FBA_A11
FBA_A12
FBA_A13
FBA_A14
FBA_A0
FBA_A1
FBA_A2
FBA_A3
FBA_A4
FBA_A5
FBA_A6
FBA_A7
FBA_A8
FBA_A9
FBA_A10
FBA_A11
FBA_A12
FBA_A13
FBA_A14
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
UV5
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D25
FBA_D28
FBA_D27
FBA_D29
FBA_D26
FBA_D30
FBA_D24
FBA_D31
+FBA_VREFCA0
+FBA_VREFDQ0
FBA_A0
FBA_A1
FBA_A2
FBA_A3
FBA_A4
FBA_A5
FBA_A6
FBA_A7
FBA_A8
FBA_A9
FBA_A10
FBA_A11
FBA_A12
FBA_A13
FBA_A14
Group3
FBA_D1
FBA_D6
FBA_D2
FBA_D5
FBA_D0
FBA_D7
FBA_D3
FBA_D4
M8
H1
Group0
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
FBA_D8
FBA_D12
FBA_D9
FBA_D10
FBA_D15
FBA_D14
FBA_D13
FBA_D11
E3
F7
F2
F8
H3
H8
G2
H7
FBA_D17
FBA_D23
FBA_D18
FBA_D20
FBA_D16
FBA_D21
FBA_D22
FBA_D19
D7
C3
C8
C2
A7
A2
B8
A3
+1.35VGS
1
2
RPV7
4
3
23,25
23,25
23,25
+FBA_VREFDQ0
1.33K_0404_4P2R_1%
RANKA@
1
2
FBA_BA0
FBA_BA1
FBA_BA2
CV216
.01U_0402_16V7-K
RANKA@
23
23
23
FBA_CLK0
FBA_CLK0#
FBA_CKE0
FBA_BA0
FBA_BA1
FBA_BA2
M2
N8
M3
FBA_CLK0
FBA_CLK0#
FBA_CKE0
J7
K7
K9
FBA_ODT0
FBA_CS0#
FBA_RAS#
FBA_CAS#
FBA_W E
K1
L2
J3
K3
L3
BA0
BA1
BA2
CK
CK
CKE
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
FBA_BA0
FBA_BA1
FBA_BA2
M2
N8
M3
FBA_CLK0
FBA_CLK0#
FBA_CKE0
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBA_ODT0
FBA_CS0#
FBA_RAS#
FBA_CAS#
FBA_W E
K1
L2
J3
K3
L3
FBA_DQS1
FBA_DQS2
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
FBA_DQM1
FBA_DQM2
E7
D3
BA0
BA1
BA2
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
CK
CK
CKE
FBA_ODT0
FBA_CS0#
FBA_RAS#
FBA_CAS#
FBA_W E
FBA_CLK0
FBA_DQS3
FBA_DQS0
F3
C7
FBA_DQM3
FBA_DQM0
E7
D3
ODT
CS
RAS
CAS
WE
DQSL
DQSU
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
ODT
CS
RAS
CAS
WE
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
DQSL
DQSU
0..31
FBA_RST#
FBA_RST#
1
1
RV131
10K_0402_5%
RANKA@
2 RV130
L8
243_0402_1%
RANKA@
J1
L1
J9
L9
M7
2
FBA_ODT0
1
1
FBA_CKE0
2
B
RV134
10K_0402_5%
RANKA@
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
FBA_RST#
T2
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
M7
RV132
243_0402_1%
RANKA@
96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@
2
RV133
10K_0402_5%
RANKA@
T2
FBA_DQS#1 G3
FBA_DQS#2 B7
1
23,25
DQSL
DQSU
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
2
1
2
FBA_DQS#3 G3
FBA_DQS#0 B7
FBA_CLK0#
DML
DMU
DML
DMU
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
DQSL
DQSU
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
32..63
CS0#
FBx_CMD1
ODT0
FBx_CMD2
Group2
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBx_CMD3
CKE0
FBx_CMD4
A14
A14
FBx_CMD5
RST
RST
FBx_CMD6
A9
A9
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE
WE
FBx_CMD14
A15
A15
FBx_CMD15
CAS#
CAS#
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
C
CS1#
FBx_CMD16
RV129
162_0402_1%
RANKA@
23,25
23,25
Rank0
Address
FBx_CMD0
C
23
23
23,25
23,25
23,25
FBA_DQS[7..0]
FBA_DQS#[7..0]
CMD mapping mod Mode D
Group1
+1.35VGS
B2
D9
G7
K2
K8
N1
N9
R1
R9
23,25
FBx_CMD17
ODT1
FBx_CMD18
CKE1
FBx_CMD19
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@
FBx_CMD20
A13
A13
FBx_CMD21
A8
A8
FBx_CMD22
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
FBx_CMD30
RAS#
RAS#
B
FBx_CMD31
FBx_CMD32
FBx_CMD33
+1.35VGS
+1.35VGS
UV6 SIDE
+1.35VGS
FBx_CMD34
DBG0
FBx_CMD35
DBG1
+1.35VGS
UV5 SIDE
RANKA@
RANKA@
RANKA@
RANKA@
CD@
@
RANKA@
RANKA@
CD@
RANKA@
2
RANKA@
2
RANKA@
1
CV139
1
CV134
1
33P_0402_50V8J
2
CV133
1
1U_0402_6.3V6K
2
CV132
1
1U_0402_6.3V6K
2
CV131
1
1U_0402_6.3V6K
2
CV130
CV129
1
1U_0603_25V6M
2
0.1U_0402_10V7K
For RF
RANKA@
1
0.1U_0402_10V7K
2
CV127
1
33P_0402_50V8J
2
CV122
CV121
1
1U_0402_6.3V6K
2
CV120
1
1U_0603_25V6M
2
CV119
1
1U_0402_6.3V6K
2
CV118
1
1U_0402_6.3V6K
2
0.1U_0402_10V7K
1
CV117
0.1U_0402_10V7K
For RF
2
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
DDR3 VRAM Rank0_L
2014/01/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
24
of
60
5
4
3
2
1
at least 16 mils width(optimal)
20 mils spacing to other signals /planes
FBA_D[0..63]
D
+1.35VGS
RPV8
4
3
UV8
+FBA_VREFCA1
1
1.33K_0404_4P2R_1%
RANKA@
2
+FBA_VREFCA1
+FBA_VREFDQ1
CV141
.01U_0402_16V7-K
RANKA@
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
+1.35VGS
1
2
RPV9
FBA_A0
FBA_A1
FBA_A2
FBA_A3
FBA_A4
FBA_A5
FBA_A6
FBA_A7
FBA_A8
FBA_A9
FBA_A10
FBA_A11
FBA_A12
FBA_A13
FBA_A14
FBA_A0
FBA_A1
FBA_A2
FBA_A3
FBA_A4
FBA_A5
FBA_A6
FBA_A7
FBA_A8
FBA_A9
FBA_A10
FBA_A11
FBA_A12
FBA_A13
FBA_A14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D53
FBA_D55
FBA_D52
FBA_D50
FBA_D48
FBA_D51
FBA_D54
FBA_D49
+FBA_VREFCA1
+FBA_VREFDQ1
Group6
FBA_D32
FBA_D39
FBA_D33
FBA_D36
FBA_D35
FBA_D38
FBA_D34
FBA_D37
M8
H1
FBA_A0
FBA_A1
FBA_A2
FBA_A3
FBA_A4
FBA_A5
FBA_A6
FBA_A7
FBA_A8
FBA_A9
FBA_A10
FBA_A11
FBA_A12
FBA_A13
FBA_A14
Group4
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
FBA_D40
FBA_D43
FBA_D41
FBA_D42
FBA_D45
FBA_D47
FBA_D44
FBA_D46
E3
F7
F2
F8
H3
H8
G2
H7
4
3
+FBA_VREFDQ1
1
2
23,24
23,24
23,24
CV217
.01U_0402_16V7-K
RANKA@
23
23
23
C
M2
N8
M3
FBA_CLK1
FBA_CLK1#
FBA_CKE1
FBA_CLK1
FBA_CLK1#
FBA_CKE1
23
23
23,24
23,24
23,24
FBA_CLK1
FBA_BA0
FBA_BA1
FBA_BA2
FBA_BA0
FBA_BA1
FBA_BA2
FBA_ODT1
FBA_CS1#
FBA_RAS#
FBA_CAS#
FBA_W E
FBA_ODT1
FBA_CS1#
FBA_RAS#
FBA_CAS#
FBA_W E
1
FBA_DQS6
FBA_DQS4
RV137
162_0402_1%
FBA_DQM6
FBA_DQM4
RANKA@
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
FBA_CLK1#
FBA_DQS#6 G3
FBA_DQS#4 B7
23,24
FBA_RST#
FBA_RST#
T2
L8
FBA_CKE1
1
J1
L1
J9
L9
M7
RV140
243_0402_1%
RANKA@
2
1
1
FBA_ODT1
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
23,24
FBA_DQS#[7..0]
23,24
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
CMD mapping mod Mode D
FBA_D57
FBA_D63
FBA_D59
FBA_D62
FBA_D56
FBA_D61
FBA_D58
FBA_D60
D7
C3
C8
C2
A7
A2
B8
A3
FBx_CMD0
0..31
32..63
CS0#
FBx_CMD1
Group7
FBx_CMD2
ODT0
FBx_CMD3
CKE0
FBx_CMD4
A14
A14
FBx_CMD5
RST
RST
FBx_CMD6
A9
A9
FBx_CMD7
A7
A7
FBx_CMD8
A2
A2
FBx_CMD9
A0
A0
FBx_CMD10
A4
A4
FBx_CMD11
A1
A1
FBx_CMD12
BA0
BA0
FBx_CMD13
WE
WE
FBx_CMD14
A15
A15
FBx_CMD15
CAS#
CAS#
+1.35VGS
FBA_BA0
FBA_BA1
FBA_BA2
B2
D9
G7
K2
K8
N1
N9
R1
R9
M2
N8
M3
FBA_CLK1
FBA_CLK1#
FBA_CKE1
A1
A8
C1
C9
D2
E9
F1
H2
H9
J7
K7
K9
FBA_ODT1
FBA_CS1#
FBA_RAS#
FBA_CAS#
FBA_W E
K1
L2
J3
K3
L3
FBA_DQS5
FBA_DQS7
F3
C7
FBA_DQM5
FBA_DQM7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
E7
D3
FBA_DQS#5 G3
FBA_DQS#7 B7
FBA_RST#
T2
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
M7
RV141
243_0402_1%
RANKA@
96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@
B
23,24
FBA_DQS[7..0]
Rank0
BA0
BA1
BA2
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
CK
CK
CKE
ODT
CS
RAS
CAS
WE
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
DQSL
DQSU
DML
DMU
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
DQSL
DQSU
RESET
ZQ
NC1
NC2
NC3
NC4
NC5
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBx_CMD16
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
C
CS1#
FBx_CMD17
FBx_CMD18
ODT1
FBx_CMD19
B1
B9
D1
D8
E2
E8
F9
G1
G9
2
2
RV138
RV139
10K_0402_5% 10K_0402_5%
RANKA@
RANKA@
DQSL
DQSU
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
Group5
Address
+1.35VGS
1.33K_0404_4P2R_1%
RANKA@
2
M8
H1
FBA_DQM[7..0]
UV7
1
1
2
2
D
23,24
96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@
CKE1
FBx_CMD20
A13
A13
FBx_CMD21
A8
A8
FBx_CMD22
A6
A6
FBx_CMD23
A11
A11
FBx_CMD24
A5
A5
FBx_CMD25
A3
A3
FBx_CMD26
BA2
BA2
FBx_CMD27
BA1
BA1
FBx_CMD28
A12
A12
FBx_CMD29
A10
A10
FBx_CMD30
RAS#
RAS#
B
FBx_CMD31
FBx_CMD32
FBx_CMD33
RANKA@
2
RANKA@
2
RANKA@
2
RANKA@
2
RANKA@
2
CD@
@
1
CV164
1
CV159
1
CV158
1
CV157
1
CV156
CV155
1
For RF
33P_0402_50V8J
2
CV154
1
1U_0603_25V6M
2
1U_0402_6.3V6K
RANKA@
1
DBG1
+1.35VGS
1U_0402_6.3V6K
2
CV152
CV147
CV146
RANKA@
1
1U_0402_6.3V6K
2
DBG0
FBx_CMD35
UV7 SIDE
0.1U_0402_10V7K
RANKA@
1
+1.35VGS
0.1U_0402_10V7K
2
For RF
33P_0402_50V8J
CD@
1
1U_0402_6.3V6K
2
CV145
CV144
CV143
RANKA@
1
1U_0402_6.3V6K
2
1U_0402_6.3V6K
RANKA@
1
1U_0603_25V6M
2
CV142
1
+1.35VGS
UV8 SIDE
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.35VGS
FBx_CMD34
2
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
DDR3 VRAM Rank0_H
2014/01/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
25
of
60
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
DDR3 VRAM Rank1_L
2014/01/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
26
of
60
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Blank
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
27
of
59
5
4
3
Physical
Strapping pin
ROM_SCLK
+3VG_AON
2
RV150
45.3K_0402_1%
@
1
Logical
Strapping Bit3
Logical
Strapping Bit2
Logical
Strapping Bit1
+3VGS
SOR3_EXPOSED
SOR2_EXPOSED
SOR1_EXPOSED
SOR0_EXPOSED
ROM_SI
+3VGS
RAM_CFG[3]
RAM_CFG[2]
RAM_CFG[1]
RAM_CFG[0]
ROM_SO
+3VGS
DEVID_SEL
PCIE_CFG
SMB_ALT_ADDR
VGA_DEVICE
STRAP0
+3VGS
STRAP1
+3VGS
STRAP2
+3VGS
STRAP3
+3VGS
STRAP4
+3VGS
Power Rail
Logical
Strapping Bit0
D
Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
1
RV149
4.99K_0402_1%
@
1
RV148
10K_0402_1%
OPT@
1
RV147
45.3K_0402_1%
@
1
1
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
2
RV155
45.3K_0402_1%
OPT@
1
RV154
4.99K_0402_1%
OPT@
1
RV153
15K_0402_1%
@
1
RV152
45.3K_0402_1%
OPT@
1
1
RV151
45.3K_0402_1%
@
2
2
Reserved(keep pull-up and pull-down footprint and not stuff by default)
2
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
2
20
20
20
20
20
2
2
2
2
D
RV146
45.3K_0402_1%
OPT@
2
+3VGS
C
DEVID_SEL
Pull-up to
+3VGS
Pull-down to Gnd
1000
0000
1001
0001
15K
1010
0010
20K
1011
0011
24.9K
SD03424928J
30.1K
SD03430128J
34.8K
SD03434828J
45.3K
SD03445328J
1100
0100
1101
0101
1110
0110
1111
0111
Resistor Values
4.99K
SD03449918J
10K
0
(Default)
1
PCIE_CFG
0
(Default)
1
C
Physical
Strapping pin
ROM_SCLK
2
RV161
10K_0402_1%
@
1
1
RV160
10K_0402_1%
@
1
RV159
10K_0402_1%
@
X76
Power Rail
0
0x9E (Default)
1
0x9C (Multi-GPU usage)
Strap Mapping
+3VGS
SMB_ALT_ADDR
ROM_SI
+3VGS
SUB_VENDOR
ROM_SO
+3VGS
VGA_DEVICE
VGA_DEVICE
STRAP0
+3VGS
RAM_CFG[0]
0
3D Device (Class Code 302h)
STRAP1
+3VGS
RAM_CFG[1]
1
VGA Device (Default)
1
RV158
4.99K_0402_1%
OPT@
ROM_SI
ROM_SO
ROM_SCLK
2
ROM_SI
ROM_SO
ROM_SCLK
2
20
20
20
RV157
4.99K_0402_1%
OPT@
1
1
RV156
4.99K_0402_1%
@
2
2
2
SMBUS_ALT_ADDR
STRAP2
+3VGS
RAM_CFG[2]
STRAP3
+3VGS
RAM_CFG[3]
STRAP4
+3VGS
PCIE_MAX_SPEED
X76
GPU
FB Memory (DDR3L)
ROM_SI
Hynix
900MHz
N16V-GM
Micron
900MHz
256M x 16
0xE
0xD
256M x 16
PU 30.1K
128M x 16
0xD
0xB
0xB
MT41J128M16JT-093G
Micron
900MHz
Samsung
900MHz
128M x 16
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
B
PU 4.99K
PU 4.99K
PU 45.3K
PD 45.3K
PU 10K
PD 4.99K
PD 45.3K
PU 20K
0x8
0x8
K4W2G1646Q-BC1A
128M x 16
ROM_SCLK
PU 34.8K
MT41J256M16HA-093G:E
H5TC2G63FFR-11C
Hynix
900MHz
ROM_SO
0xE
H5TC4G63AFR-11C
B
PU 4.99K
0x7
0x7
PD 45.3K
VRAM
Samsung
X76
VRAM P/N
X7606012101
SA00005SH40
X7606012001
SA00005M120
X7606012002
SA00005VS00
Micron
A
A
Hynix
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
N16X_MISC
2014/01/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
28
of
60
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Blank
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
29
of
59
5
4
3
2
1
D
D
UW 1
9
9
RW 2 1
RW 9 1
RW 10 1
USB20_N3
USB20_P3
USB20_N3
USB20_P3
@
@
2 6.2K_0402_1%
2 0_0402_5%
2 0_0402_5%
2
USB20_N3
USB20_P3
LW 1
1
4
EMC@
1
2
4
3
USB20_N3_R
2
1
2
CARD_3V3
SDREG
CW 3
CW 4
1U_0402_6.3V6K
1
0.1U_0402_10V7K
CW 2
4.7U_0603_6.3V6K
+3VS
RREF
USB20_N3_R
USB20_P3_R
SD_W P
1
2
SD_D1_R
SD_D0_R
1
2
3
4
5
6
7
8
9
10
11
12
25
RREF
DM
DP
3V3_IN
CARD_3V3
SDREG
XD_CD#
SP1
SP2
SP3
SP4
SP5
V18
XD_D7
SP14
SP13
SP12
SP11
SP10
GPIO0
SP9
SP8
SP7
SP6
24
23
22
21
20
19
18
17
16
15
14
13
VDD18
1U_0402_6.3V6K 2
1
CW 1
SD_D2_R
SD_D3_R
SD_CMD_R
SD_CLK_R
SD_CD#
GND
USB20_P3_R
3
RTS5170-GRT_QFN24_4X4
EXC24CH900U_4P
CARD_3V3
FOR EMI
SD_D3_R
RW 6 1
2
EMC@
SD_CMD_R RW 7 1
2
EMC@
SD_CLK_R
RW 8 1
SD_D1
CARD_3V3
2 .1U_0402_10V6-K
SD_D2
2 .1U_0402_10V6-K
SD_D3
2 .1U_0402_10V6-K
SD_CMD
2 5.6P_0402_50V8-D
2 15_0402_5%
EMC@
2 5.6P_0402_50V8-D
EMC@
CW 12 1
SD_CLK
DW 1
EMC_NS@
CW 9
2
SD_D0
SD_D1
SD_D2
SD_D3
1
CW 10
2
Close to Connector
5P_0402_50V8-C
2
EMC@
1
.1U_0402_10V6-K
2
EMC@
4
Close to Connector
4.7U_0603_6.3V6K
RW 5 1
FOR ESD
2 .1U_0402_10V6-K
1
RW 4 1
SD_D2_R
CW 5 1
EMC_NS@
0_0402_5%
CW 6 1
EMC_NS@
0_0402_5%
CW 7 1
EMC_NS@
0_0402_5%
CW 8 1
EMC_NS@
15_0402_5%
CW 11 1
1
SD_D1_R
JREAD1
SD_D0
2 0_0402_5%
EMC@
EMC@
Close to UW1 Placement
1
7
8
9
1
SD_CD#
SD_W P
11
10
SD_CMD
SD_CLK
2
5
2
RW 3 1
2
SD_D0_R
AZ5425-01F_DFN1006P2E2
C
3
6
CW 13
EMC_NS@
2
C
VDD
DAT0
DAT1
DAT2
CD/DAT3
C/D
W/P
CMD
CLK
VSS1
VSS2
GND_1
GND_2
12
13
DEREN_404232501111RHF_NR
ME@
SD / MMC
Close to Connector
CW11,CW12 need to change 5.6pf CAP as EMC request
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
2015/12/11
Cardreader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
3
2
1
Sheet
30
of
60
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Blank
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
31
of
59
5
4
3
2
1
D
D
+3VS
+3VS_TPM
1A
1
TPM
2
RTPM11 TPM@
2 0_0603_5%
1
CTPM4
.1U_0402_10V6-K
TPM@
2
1
CTPM1
10U_0603_6.3V6M
TPM@
2
CTPM3
.1U_0402_10V6-K
TPM@
C
C
+3VS_TPM
UTPM1
1
2
3
7
6
9
4
11
18
+3VS_TPM
5
8
12
13
14
B
NC_1
NC_2
NC_3
PP
NC_4
VNC_1
GND_1
GND_2
GND_3
NC_5
VNC_2
NC_6
NC_7
NC_8
TPM@
VPS_1
VPS_2
LPCPD#
SERIRQ
LAD0
LAD1
LFRAME#
LAD2
LAD3
NC_11
LCLK
NC_10
NC_9
LRESET#
24
10
RTPM2 1 TPM@ 2
SERIRQ_TPM
RTPM5
LPC_AD0_TPM
RTPM6
LPC_AD1_TPM
RTPM7
LPC_FRAME#_TPM
RTPM8
LPC_AD2_TPM
RTPM9
LPC_AD3_TPM
RTPM10
28
27
26
23
22
20
17
4.7K_0402_5%
1 TPM@ 2 0_0402_5%
1 TPM@ 2 0_0402_5%
1 TPM@ 2 0_0402_5%
1 TPM@ 2 0_0402_5%
1 TPM@ 2 0_0402_5%
1 TPM@ 2 0_0402_5%
SERIRQ
LPC_AD0
LPC_AD1
LPC_FRAME#
LPC_AD2
LPC_AD3
9,44
7,44
7,44
7,44
7,44
7,44
+3VS_TPM
25
21
19
15
CLK_PCI_TPM
RTPM4
1 TPM@
16
8
2 0_0402_5%
PLT_RST#
8,19,37,40,44
B
ST33ZP24AR28PVSP_TSSOP28
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
TPM
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
32
of
59
5
4
3
2
1
LCD POWER CIRCUIT
CMOS Camera
+3VS
+LCDVDD_CON
+5VS
+3VS_CMOS
U5
D
GND
PCH_ENVDD
4
EN
FLG
J1
2
3
2
AP22802AW 5-7_SOT25-5
U5 EN PIN VIH MIN 1.5V
2
1
1
2
@
W=40 mils
1
W=40mils
2
2
JUMP_43X39
1
2
+3VS
0_0805_5%
2
1
1
C3
.1U_0402_10V6-K
CD@
2
C4
10U_0603_6.3V6M
@
D
R277
@
For RF
PCH_ENVDD
PCH_ENVDD
2
1
@
1
4
1
33P_0402_50V8J
C123
1
C1
.1U_0402_10V6-K
Need short
W=60mils
1
EMC_NS@
OUT
.1U_0402_10V6-K
C122
IN
4.7U_0603_6.3V6K
C121
5
2
R1
100K_0402_5%
EMI request
EMC_NS@
R10
4.7K_0402_5%
@
B+
R14
1
@
2 0_0402_5%
ENBKL
R16
100K_0402_5%
ENBKL
44
R17
2A 80 mil
C14
1
2
2
0_0805_5%
2
1
CD@
1
R13
100K_0402_1%
R15
100K_0402_1%
@
@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
+LEDVDD
2
CPU_EDP_TX0+
CPU_EDP_TX0-
4
4
CPU_EDP_TX1+
CPU_EDP_TX1-
2
4
4
4
4
CPU_EDP_AUX
CPU_EDP_AUX#
CPU_EDP_TX0+
CPU_EDP_TX0-
C19
C16
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_TX0+
EDP_TX0-
CPU_EDP_TX1+
CPU_EDP_TX1-
C17
C18
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_TX1+
EDP_TX1-
CPU_EDP_AUX
C20
CPU_EDP_AUX# C21
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_AUX
EDP_AUX#
DISPOFF#
1
1
2 0_0402_5%
C13
JEDP1
EMI Request
INVT_PW M
INVT_PW M
@
4
1
R19
2
2
R18
1K_0402_5%
@
PCH_EDP_PW M
1
C
EMC@
+3VS
4
EMC_NS@
C15
1
DISPOFF#
1
2 0_0402_5%
1
1
BKOFF#
PCH_ENBKL
@
0.1U_0402_25V6
4
1
2
2
2A 80 mil
R12
1
EDP_AUX
EDP_AUX#
+LEDVDD
4.7U_0805_25V6-K
44
C
INVT_PW M
DISPOFF#
470P_0402_50V7K
@
C12
@
470P_0402_50V7K
R9
100K_0402_1%
1
R8
100K_0402_1%
2
1
+3VS
2
2
+3VS
CPU_EDP_HPD
R20
100K_0402_5%
W=60mils
+LCDVDD_CON
+3VS
2
43
43
DMIC_DATA
DMIC_CLK
9
9
B
USB20_P5
USB20_N5
R182 1
R183 1
+3VS_CMOS
2 0_0402_5% USB20_P5_R
2 0_0402_5% USB20_N5_R
2
C24
0.047U_0402_16V7K
EMC_NS@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
G1
G2
G3
G4
G5
31
32
33
34
35
B
ACES_50406-03071-001
ME@
W=40mils
1
EMI request
For EMI
L12
USB20_P5
1
USB20_N5
4
EMC_NS@
1
2
4
3
2
USB20_P5_R
3
USB20_N5_R
CMM21T-900M-N_4P
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
eDP/ CMOS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, May 11, 2015
Date:
3
2
Rev
0.2
CG510
Sheet
1
33
of
59
5
4
L2
HDMI_CLK-_C
1
HDMI_CLK+_C
4
3
2
1
EMC@
1
2
4
3
2
HDMI_CLK-_CON
3
HDMI_CLK+_CON
EXC24CH900U_4P
+3VS
EXC24CH900U_4P
4
HDMI_TX0-_C
1
HDMI_TX1-_C
1
4
3
1
L3
2
EMC@
L4
EMC@
D
3
HDMI_TX0+_CON
2
HDMI_TX0-_CON
G
HDMI_TX0+_C
5
D
HDMI_DET
D3
1 1
10 9
HDMI_DET
HDMIDAT_R
2 2
9 8
HDMIDAT_R
HDMICLK_R
4 4
7 7
HDMICLK_R
+5VS_HDMI
5 5
6 6
+5VS_HDMI
Q1B
DDPB_CLK
HDMI_TX1+_CON
3
L5
4
1
2
4
3
2
HDMI_TX2-_CON
3
HDMI_TX2+_CON
4
1
DDPB_DATA
HDMIDAT_R
6
D
HDMI_TX2+_C
3 3
EMC@
S
1
HDMICLK_R
Q1A
EXC24CH900U_4P
HDMI_TX2-_C
3
2N7002KDWH_SOT363-6
2
3
4
4
G
4
HDMI_TX1-_CON
2
D
4
2
S
HDMI_TX1+_C
1
8
2N7002KDWH_SOT363-6
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@
EXC24CH900U_4P
For EMC
C
C
R29
1
2 470_0402_5%
HDMI_CLK+_C
R30
1
2 470_0402_5%
HDMI_TX0-_C
R31
1
2 470_0402_5%
HDMI_TX0+_C
R32
1
2 470_0402_5%
HDMI_TX1-_C
R33
1
2 470_0402_5%
HDMI_TX1+_C
R34
1
2 470_0402_5%
HDMI_TX2-_C
R37
1
2 470_0402_5%
HDMI_TX2+_C
R38
1
2 470_0402_5%
+5VS
+5VS_HDMI_F
2
D4
1
3
Q22
2
G
46
SUSP
C34
.1U_0402_10V6-K
2
RP1
2
2N7002KW_SOT323-3
2N7002KW_SOT323-3
1
2
R41
20K_0402_5%
2.2K_0404_4P2R_5%
S
JHDMI1
HDMI_DET
1
3
@
4
3
1
1
Q13
1
D
S
G
1
2
LP2301ALT1G_SOT23-3
BAT54S-7-F_SOT23-3
D
2
G
D
3
HDMI_HPD
2
R42
1
0.5A_8V_KMC3S050RY
1
4
+3VS
D4
1
2
@
Q12
F1
1
3
RB491D_SOT23-3
@
2
3
+3VS
R35
1M_0402_5%
+5VS_HDMI
D5
+5VS
S
HDMI_CLK-_C
2
HDMIDAT_R
HDMICLK_R
100K_0402_5%
B
4
HDMI_CLK-
4
4
HDMI_CLK+
HDMI_TX0-
4
4
HDMI_TX0+
HDMI_TX1-
4
4
HDMI_TX1+
HDMI_TX2-
4
HDMI_TX2+
HDMI_CLK-
C35
2
1 .1U_0402_10V6-K
HDMI_CLK-_C
R43 2
@
1 0_0402_5%
HDMI_CLK-_CON
HDMI_CLK+
HDMI_TX0-
C36
C37
2
2
1 .1U_0402_10V6-K
1 .1U_0402_10V6-K
HDMI_CLK+_C R44 2
HDMI_TX0-_C R45 2
@
@
1 0_0402_5%
1 0_0402_5%
HDMI_CLK+_CON
HDMI_TX0-_CON
HDMI_TX0+
HDMI_TX1-
C38
C39
2
2
1 .1U_0402_10V6-K
1 .1U_0402_10V6-K
HDMI_TX0+_C R46 2
HDMI_TX1-_C R47 2
@
@
1 0_0402_5%
1 0_0402_5%
HDMI_TX0+_CON
HDMI_TX1-_CON
HDMI_TX1+
HDMI_TX2-
C40
C41
2
2
1 .1U_0402_10V6-K
1 .1U_0402_10V6-K
HDMI_TX1+_C R48 2
HDMI_TX2-_C R49 2
@
@
1 0_0402_5%
1 0_0402_5%
HDMI_TX1+_CON
HDMI_TX2-_CON
HDMI_TX2+
C42
2
1 .1U_0402_10V6-K
HDMI_TX2+_C R50 2
@
1 0_0402_5%
HDMI_TX2+_CON
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND1
CK_shield GND2
CK+
GND3
D0GND4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
B
SINGA_2HE3Y37-000111F
ME@
Close to JHDMI1
A
HDMI_TX0-_CON
D6
1 1
10 9
HDMI_TX0-_CON
HDMI_TX1-_CON
D7
1 1
10 9
HDMI_TX1-_CON
HDMI_TX0+_CON
2 2
9 8
HDMI_TX0+_CON
HDMI_TX1+_CON
2 2
9 8
HDMI_TX1+_CON
HDMI_CLK-_CON
4 4
7 7
HDMI_CLK-_CON
HDMI_TX2-_CON
4 4
7 7
HDMI_TX2-_CON
HDMI_CLK+_CON
5 5
6 6
HDMI_CLK+_CON
HDMI_TX2+_CON
5 5
6 6
HDMI_TX2+_CON
3 3
3 3
8
8
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@
For EMC
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
3
2
Sheet
1
34
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
2015/02/27
2013/08/05
Deciphered Date
Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
3
2
Sheet
1
35
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
3
2
Sheet
1
36
of
59
5
4
3
2
1
+3VALW TO +3VALW_LAN
+3VALW
Need short
1
JL1
1
+3VALW_LAN rising time (10%~90%):
0.5ms＜spec＜100ms
+3VALW_LAN
2
+3VALW_LAN
width : 40 mils
2 @
+LAN_VDDREG
1
RL1
@
2 0_0603_5%
JUMP_43X79
D
CL5
@
Close to Pin11
2
Close to Pin32
CL6
2
1
CL7
2
Close to Pin11
.1U_0402_10V6-K
2
1
.1U_0402_10V6-K
@
1
4.7U_0603_6.3V6K
CL4
4.7U_0603_6.3V6K
1
1
CL1
4.7U_0603_6.3V6K
2
1
2
D
CL2
.1U_0402_10V6-K
CD@
Close to Pin32
UL1
LAN_CLKREQ#_R
44
RL6 1
LAN_WAKE#
@
2 0_0402_5%
1
2
2.49K_0402_1%
+3VALW_LAN
TL3 @ 1
2
RL8
TL4 @ 1
+3VALW_LAN
RSET
+LAN_VDD10
LAN_XTALO
LAN_XTALI
1
LAN_DISABLE#
RL21
10K_0402_5%
@
1
2
RL9
1K_0402_1%
8,19,32,40,44
9
9
LAN_DISABLE#
1
ISOLATE#
PLT_RST#
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
2
1
2
LAN_CLKREQ#
8,9
CL10 1
CL11 1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
+LAN_REGOUT
+LAN_VDDREG
+LAN_VDD10
PCIE_WAKE#_R
ISOLATE#
PLT_RST#
PCIE_PRX_C_DTX_N3
PCIE_PRX_C_DTX_P3
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
AVDD33_2
RSET
AVDD10
CKXTAL2
CKXTAL1
LED0
LED1/GPIO
LED2
REGOUT
VDDREG
DVDD10
LANWAKEB
ISOLATEB
PERSTB
HSON
HSOP
REFCLK_N
REFCLK_P
HSIN
HSIP
CLKREQB
AVDD33_1
MDIN3
MDIP3
AVDD10_2
MDIN2
MDIP2
MDIN1
MDIP1
AVDD10_1
MDIN0
MDIP0
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3
LAN_CLKREQ#_R
+3VALW_LAN
LAN_MDI3LAN_MDI3+
+LAN_VDD10
LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
+LAN_VDD10
LAN_MDI0LAN_MDI0+
CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3
LAN_MDI3LAN_MDI3+
38
38
LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
38
38
38
38
LAN_MDI0LAN_MDI0+
38
38
C
8
8
9
9
CL10 close to Pin18
CL11 close to Pin17
PLT_RST#
RL11
15K_0402_5%
@
2
1
@
0_0402_5%
PCIE_WAKE#_R
C
+3VS
RL18
CL34
.1U_0402_10V6-K
EMC_NS@
RTL8111GUL-CG_QFN32_4X4
@
100M LAN
B
B
For RTL8111GUL/ RTL8106EUL (SWR mode)
LAN_XTALI
1
2
CL12
10P_0402_50V8J
LAN_XTALO
OSC1
GND2
GND1
OSC2
RL20
1
2 0_0805_5%
4
+LAN_REGOUT
1
2
LL1
2.2UH_NLC252018T-2R2J-N_5%
3
1
1
1
25MHZ_10PF_7V25000014
2
+LAN_VDD10
@
YL1
CL13
10P_0402_50V8J
2
2
1
CL33
CL15
.1U_0402_10V6-K
4.7U_0603_6.3V6K
@
2
1
2
1
CL16
.1U_0402_10V6-K
CD@
2
1
CL17
.1U_0402_10V6-K
2
1
CL18
.1U_0402_10V6-K
2
1
CL19
.1U_0402_10V6-K
2
1
CL20
.1U_0402_10V6-K
Close to Pin3, 8, 22, 30
2
1
CL21
1U_0402_6.3V6K
@
2
CL22
.1U_0402_10V6-K
@
Close to Pin30(Reserved)
Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
LAN_RTL8106EUL
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Thursday, May 14, 2015
Sheet
1
37
of
59
5
4
3
2
1
DL1/DL2
1'S PN:SC300003M00
2
9
LAN_MDI2-
GND
NC5
NC1
I/O4
DL1
37
LAN_MDI0+
LAN_MDI0+
22
8
21
11
10
3
I/O2
EMC_NS@
37
LAN_MDI1-
37
LAN_MDI1+
LAN_MDI1-
20
LAN_MDI1+
19
LAN_MDI3-
18
37
LAN_MDI2+
37
LAN_MDI2-
LAN_MDI2+
17
LAN_MDI2-
16
15
DL2
LAN_MDI1+
C
+3VALW_LAN
9
2
4
5
6
LAN_MDI1-
7
I/O4
NC1
EMC_NS@
3
I/O2
NC5
NC2
VDD
GND
NC3
NC4
I/O3
I/O1
37
LAN_MDI0+
1
10
2
11
37
CL24
68P_0402_50V8J
EMC@
LAN_MDI3+
LAN_MDI3-
LAN_MDI3+
LAN_MDI3-
14
13
TCT1
MX1+
TD1+
MX1-
TD1-
MCT2
TCT2
MX2+
TD2+
MX2-
TD2-
MCT3
TCT3
MX3+
TD3+
MX3-
TD3-
MCT4
TCT4
MX4+
MX4-
TD4+
TD4-
1
MCT
2
LAN_MDO0-
3
LAN_MDO0+
4
MCT
5
LAN_MDO1-
6
LAN_MDO1+
7
MCT
8
LAN_MDO2+
9
LAN_MDO2-
10
MCT
11
LAN_MDO3+
12
LAN_MDO3-
D
RL17
20_0603_5%
EMC@
1
VDD
NC2
LAN_MDI3+
23
1
NC4
LAN_MDI0-
2
5
4
+3VALW_LAN
NC3
LAN_MDI0-
DL3
PDT5061_DO-214AA
EMC_NS@
2
6
37
1
LAN_MDI2+
AZ3033-04F_DFN2525P10E10
7
1
I/O3
I/O1
@
MCT1
2
TL1
24
D
CL32
0.022U_0603_50V7K
EMC@
1
1
2
2
CL25
1000P_1206_2KV7-K
EMC@
C
GST5009 LF
8
1
LAN_MDI0-
100M LAN
CHASSIS1_GND
AZ3033-04F_DFN2525P10E10
Place Close to TL1
JRJ1
B
RL14 1
@
LAN_MDO0+
1
LAN_MDO0-
2
LAN_MDO1+
3
LAN_MDO2+
4
LAN_MDO2-
5
LAN_MDO1-
6
LAN_MDO3+
7
LAN_MDO3-
8
2 0_0603_5%
RL15 1
@
2 0_0603_5%
RL16 1
@
2 0_0603_5%
PR1+
PR1PR2+
PR3+
B
PR3PR2PR4+
PR4GND_1
GND_2
9
10
CHASSIS1_GND
Reserve for EMI go rural solution
CHASSIS1_GND
ALLTO_C100JH-10839-L
ME@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
LAN_Transformer
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
CG510
Wednesday, May 13, 2015
Sheet
1
38
of
59
5
4
3
2
1
D
D
+3VALW
+3VALW
Near CPU
1
1
Near GPU&VRAM
R36
13.7K_0402_1%
OPT@
NTC_V2
1
2
2
R25
13.7K_0402_1%
1
NTC_V1
PH2
100K_0402_1%_NCP15WF104F03RC
OPT@
2
2
2
2
PH3
100K_0402_1%_NCP15WF104F03RC
R253
0_0402_5%
@
1
1
R257
0_0402_5%
OPT@
C
C
EC_AGND
+5VLP
+5VLP
for layout optimized, change the EC_AGND to GND
R252
21.5K_0402_1%
@
0.1U_0402_25V6
@
R255
21.5K_0402_1%
@
1
2
2
2
HW thermal sensor
C189
@
1
1
+5VLP
U4
1
2
54
3
EC_ON_R
4
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
8
TMSNS1
7
PHYST1
6
TMSNS2
5
OT2 RHYST2
G718TM1U_SOT23-8
PHYST2
R256 1
@
2 10K_0402_5%
R254 1
@
2 10K_0402_5%
R196 1
@
2 0_0402_5%
NTC_V1
R197 1
@
2 0_0402_5%
NTC_V2
NTC_V1
44
NTC_V2
44
over temperature threshold:
RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C
B
B
FAN Conn
+5VS
JFAN1
R52
1
C49
10U_0805_10V6K
2
1
@
2 0_0603_5%
C50
.1U_0402_10V6-K
@
44
1 44
2
+5VS_FAN
EC_FAN_SPEED
EC_FAN_PWM
1
2
3
4
5
6
1
2
3
4
GND1
GND2
ACES_85205-04001
ME@
A
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
2015/02/27
Deciphered Date
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thermal sensor/FAN CONN
Size
Document Number
Custom
Date:
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
39
of
59
A
B
C
D
E
1
1
Mini-Express Card(WLAN/WiMAX)
Need short
+3VS
J2
1
1
+3VS_W LAN
@
2
2
JUMP_43X79
+3VS_W LAN
+1.5VS
R269
9
2
8
9
9
9
9
1
BT_OFF#
R53
CLK_PCIE_W LAN#
CLK_PCIE_W LAN
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4
+3VS_W LAN
44 EC_TX
44 EC_RX
EC_TX R184
EC_RX R185
1
1
@
2 0_0402_5%
2 0_0402_5%
BT_DISABLE#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
53
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
53
54
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
R80
0_0603_5%
@
+1.5VS_W LAN
2
PCH_W LAN_OFF#
9
PLT_RST#
8,19,32,37,44
+3VS_W LAN
PLT_RST#
R270
SMB_CLK_S3_R
SMB_DATA_S3_R
1
@
2 0_0402_5%
R263
R88
1
1
2 @ 0_0402_5%
2 @ 0_0402_5%
USB20_N6
USB20_P6
SMB_CLK_S3
SMB_DATA_S3
7,15
7,15
9
9
54
ARGOS_MPCET-S5201-TP40
ME@
1
R94
100K_0402_5%
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
C1107
0.047U_0402_16V4Z
@
For RF request
JW LAN1
1K_0402_5% 2
PCH_BT_OFF#
W LAN_CLKREQ#
8
8
2
2 BT_DISABLE#
1K_0402_5%
2
1
1
1
3
3
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
PCIe WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
D
Sheet
E
40
of
59
A
B
C
D
E
C55
1
+5VALW
5
1
1
IN
C128
1U_0402_6.3V6K
2 44
+USB_VCCA
U2
OUT
GND
USB_ON#
4
EN
FLG
2
1
1
C1108
22U_0805_6.3V6M
2
C1109
22U_0805_6.3V6M
1
@
+
+USB_VCCA
LEFT SIDE USB PORT X2
C56
@
1
C57
@
1
2
220U_6.3V_M
2
1U_0603_25V6M
2
470P_0402_50V7K
1
2
JUSB1
USB_OC1#
3
AP22802BW5-7_SOT25-5
Low Active 2A
1
2
USB_OC1#
9
9
9
C140
1000P_0402_50V7K
EMC_NS@
USB20_N0
USB20_P0
USB20_N0
USB20_P0
R65
R64
1
1
@
@
1
2
3
4
USB20_N0_R
USB20_P0_R
2 0_0402_5%
2 0_0402_5%
VBUS
DD+
GND
GND1
GND2
GND3
GND4
5
6
7
8
ALLTO_C107X3-10439-L
ME@
USB20_P0_R
+USB_VCCA
4
4
2
3
2
USB20_N0_R
3
USB20_P0_R
EMC_NS@
1
1
2
2
1
1
2
1
1
EMC_NS@
D11
EMC_NS@
2
USB20_P0
1
AZ5425-01F_DFN1006P2E2
1
D10
2
USB20_N0
EMC@
AZ5425-01F_DFN1006P2E2
L8
D9
2
2
2
AZ5425-01F_DFN1006P2E2
USB20_N0_R
EXC24CH900U_4P
USB20_P1_R
5 USB30_TX_R_P1
3
3
EXC24CH900U_4P
USB30_RX_N1
2
2
1
1
USB30_RX_R_N1
4
USB30_RX_R_P1
8
USB30_RX_P1
3
3
L9
4
EMC@
AZ1045-04F_DFN2510P10E-10-9
3
D13
EMC_NS@
D14
1
4 USB30_TX_R_N1
5
2
4
6
1
7
USB30_TX_R_P1 6
2
USB30_TX_R_N1 7
USB20_N1_R
AZ5425-01F_DFN1006P2E2
2 USB30_RX_R_P1
1
2
1
9
2
USB30_RX_R_P1 8
2
EMC_NS@
1 1USB30_RX_R_N1
AZ5425-01F_DFN1006P2E2
D12
USB30_RX_R_N1 9 10
EMC_NS@
3
For EMC
EXC24CH900U_4P
USB30_TX_C_N1 2
2
1
1
USB30_TX_R_N1
4
USB30_TX_R_P1
+USB_VCCA
USB30_TX_C_P1 3
3
L10
L11
USB20_P1
1
USB20_N1
4
4
EMC@
EMC@
1
2
4
3
2
USB20_P1_R
3
USB20_N1_R
C62
@
1
2
1U_0603_25V6M
C63
@
1
2
470P_0402_50V7K
JUSB2
EXC24CH900U_4P
9
USB30_TX_P1
9
9
For EMC
9
USB30_TX_N1
USB20_P1
9
USB20_N1
USB30_RX_P1
9
USB30_RX_N1
USB30_TX_P1 C64
1
2 .1U_0402_10V6-K
USB30_TX_C_P1 R68
1
@
2 0_0402_5%
USB30_TX_R_P1
USB30_TX_N1 C65
USB20_P1
1
2 .1U_0402_10V6-K
USB30_TX_C_N1 R69
R70
1
1
@
@
2 0_0402_5%
2 0_0402_5%
USB30_TX_R_N1
USB20_P1_R
USB20_N1
USB30_RX_P1
R71
R72
1
1
@
@
2 0_0402_5%
2 0_0402_5%
USB20_N1_R
USB30_RX_R_P1
USB30_RX_N1
R73
1
@
2 0_0402_5%
USB30_RX_R_N1
9
1
8
3
7
2
6
4
5
ME@
StdA_SSTX+
VBUS
StdA_SSTXD+
GND_DRAIN
DStdA_SSRX+
GND_5
StdA_SSRX-
GND_1
GND_2
GND_3
GND_4
10
11
12
13
SUYIN_020053GR009M2736L
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
USB2.0/USB3.0 PORT (LEFT)
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
C
D
Saturday, May 09, 2015
Rev
0.2
CG510
Sheet
E
41
of
59
A
B
C
D
E
F
G
H
SATA HDD Conn.
FOR 14"
JHDD1
7
7
1
7
7
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
C66
C67
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C68
C69
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
+5VS
J3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+5VS_HDD
Need short
1
1
2
3
4
5
6
7
@
1
2
2
JUMP_43X79
+5VS_HDD
1
2
C74
1000P_0402_50V7K
EMC_NS@
1
2
C75
.1U_0402_10V6-K
1
2
C76
1U_0402_10V6K
CD@
1
C77
10U_0805_10V6K
2
1
2
C78
10U_0805_10V6K
@
SATA ODD Conn.
GND_1
A+
AGND_2
BB+
GND_3
1
JODD1
7
7
V33_1
V33_2
V33_3
GND_4
GND_5
GND_6
V5_1
V5_2
V5_3
GND_7
DAS/DSS
GND_8
V12_1
GND1
V12_2
GND2
V12_3
7
7
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
14@ C70
14@ C71
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PTX_C_DRX_P1_14
SATA_PTX_C_DRX_N1_14
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
14@ C72
14@ C73
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PRX_C_DTX_N1_14
SATA_PRX_C_DTX_P1_14
+5V_ODD
1
2
3
4
5
6
7
8
9
10
11
12
13
GND_1
RX+
RXGND_2
TXTX+
GND_3
DP
+5V_1
+5V_2
MD
GND_4 GND1
GND_5 GND2
14
15
ALLTO_C185T1-11339-L
ME@
23
24
ALLTO_C166FE-12239-L
ME@
FOR 15"
2
2
SATA ODD FFC Conn
For EMC
JODD2
+5V_ODD
+5VS
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
15@ C82
15@ C81
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PRX_C_DTX_P1_15
SATA_PRX_C_DTX_N1_15
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
15@ C80
15@ C79
1
1
2 .01U_0402_16V7-K
2 .01U_0402_16V7-K
SATA_PTX_C_DRX_N1_15
SATA_PTX_C_DRX_P1_15
+5V_ODD
Need Short
1
2
3
4
5
6
7
8
9
10
J4
2
1
3
C85
2
1
C86
2
2
ACES_51524-00801-001
ME@
.1U_0402_10V6-K
1
JUMP_43X79
10U_0805_10V6K
1
1
2
3
4
5
6
7
8
GND_1
GND_2
3
CD@
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
HDD/ODD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
E
F
G
Sheet
42
H
of
59
5
4
3
2
1
+3VS
+3VS
+3VL
+3.3VD
.1U_0402_10V6-K
CA3
Close to Pin7
DA1
BEEP#
PC_BEEP1
9
3
PCH_BEEP
CA2
.1U_0402_10V6-K
1
2
PC_BEEP
UA1
1
1
RA14
10K_0402_5%
HDA_RST_AUDIO#
7
HDA_RST_AUDIO#
7
HDA_BITCLK_AUDIO
2
BAT54CW_SOT323-3
HDA_BITCLK_AUDIO
7
7
7
MIC1
RA44 2
OUTPUT
A MIC
C
GND
9
1
CA37 1
2
33
33
1 2.2K_0402_5%
5
HDA_SYNC_AUDIO
RA16
1
2 SDATA_IN
HDA_SDOUT_AUDIO
HDA_SYNC_AUDIO
33_0402_5%
HDA_SDIN0
HDA_SDOUT_AUDIO
DMIC_CLK
DMIC_DATA
NEIM1000032_2P
6
4
PC_BEEP
SPKR_MUTE#
10
39
JSENSE
38
37
MICBIASC
2 1U_0402_6.3V6K
8
2 100_0402_5%
RA40 1
33_0402_5% 1 RA18
2 DMIC_CLK_R
1
2 DMIC_DATA_R
RA19
@
0_0402_5%
@
.1U_0402_10V6-K
1
2
+5VD
CA13
36
40
1
11
+3.3VD
2 1U_0402_6.3V6K
CA17 1
2 2.2U_0603_6.3V6K
19
20
21
2
41
RA15
5.11K_0402_1%
@
C186 1
2 .1U_0402_10V6-K
@
C187 1
2 .1U_0402_10V6-K
@
C188 1
2 .1U_0402_10V6-K
SYNC
AVDD_3.3
VREF_1.65V
AVDD_5V
SDATA_IN
SDATA_OUT
CX11802
PC_BEEP
SPKR_MUTE#
LEFT+
LEFT-
JSENSE
GPIO1/PORTC_R_MIC
RIGHT+
RIGHT-
MUSIC_REQ/GPIO0/PORTC_L_MIC
DMIC_CLK/MUSIC_REQ/GPIO0
DMIC_DAT/GPIO1
MICBIASC
MICBIASB
PORTB_R_LINE
PORTB_L_LINE
CLASS-D_REF
PORTD_A_MIC
PORTD_B_MIC
FILT_1.8V
DVDD_IO
27
29
28
AVDD_3.3
VREF_1.65V
+5VA
12
14
SPK_L+
SPK_L-
CD@
+3.3VD
LPWR_5.0
RPWR_5.0
HGNDA
HGNDB
FLY_P
FLY_N
AVDD_HP
AVEE
PORTA_R
PORTA_L
GND
2
1
1
2
35
34
MICBIASC
MICBIASB
33
32
LINE_B_R
LINE_B_L
30
31
PORTD_A_MIC
PORTD_B_MIC
25
26
RING2_CONN
RING3_CONN
24
AVDD_HP
23
22
HPOUT_R
HPOUT_L
.1U_0402_10V6-K
CA12
Close to Pin27
17
15
MICBIASB
2
1
1
2
2
1
1
2
Close to Pin29
C
RPA2
100_0404_4P2R_1%
RA38
3K_0402_1%
EC_MUTE#
CA14 1
BIT_CLK
3
7
2
18
2
RA37
44
SPKR_MUTE#
2
RA35 1
@
0_0402_5%
FILT_1.8V
VDD_IO
VDDO_3.3
DVDD_3.3
1
CA16 close to Pin18
CA17 close to Pin2
1
3K_0402_1%
13
16
EC_MUTE#
RESET#
2
n
44
2
D
Close to Pin28 Close to Pin24
2.2U_0603_6.3V6K
CA6
+5VD
1U_0402_6.3V6K
CA10
2 0_0603_5%
CA5
.1U_0402_10V6-K
@
1
CA9
.1U_0402_10V6-K
RA10 1
Close to Pin3
1
LINE_B_R
LINE_B_L
+5VA
2
4
3
2 0_0603_5%
1
1
2
@
2
1U_0402_6.3V6K
CA8
1
RA7
D
AVDD_HP
+5VA
2
CA7
.1U_0402_10V6-K
CA1
AVDD_HP
2 0_0603_5%
@
1
+5VS
1
RA43
.1U_0402_10V6-K
CA11
DVDD_IO
2 0_0402_5%
1
@
2
RA11 1
2
2 0_0603_5%
@
CA4
4.7U_0603_10V6-K
1
.1U_0402_10V6-K
RA2
1 1
CA35
4.7U_0603_10V6-K
2 2
CA36
4.7U_0603_10V6-K
RPA3
1
2
HP_OUTR
HP_OUTL
4
3
1
82.5_0404_4P2R_1%
1
2
5.11K_0402_1%
1
2
10K_0402_1%
RA17
1
2
39.2K_0402_1%
RA36
1
2
20K_0402_1%
RPA1
PORTD_A_MIC
PORTD_B_MIC
CX11802-33Z_QFN40_5X5
2
1
RA45
3
4
2 2.2U_0603_6.3V6K RING3_CONN
2 2.2U_0603_6.3V6K RING2_CONN
CA20 1
CA21 1
100_0404_4P2R_1%
RA1
1
@
2 0_0402_5%
RA4
1
@
2 0_0402_5%
RA6
1
@
2 0_0402_5%
RA9
1
@
2 0_0402_5%
RA12
1
@
2 0_0402_5%
RA13
1
@
2 0_0402_5%
RA46
FOR ESD
1
2
CA31
2
1
EMC@
Close to Connector
ACES_50273-0020N-001
ME@
B
EMC@
3
1
@
5
6
1
1
HP_OUTR
R191 1
RING2_CONN
2
R188 1
0_0402_5% @
2
R189 1
0_0402_5% @
A_HP_OUTL_R
A_HP_OUTR_R
2015/02/27
2013/08/05
Deciphered Date
C182
1
2
1
EMC@
2
2
4
G1
LOTES_AJAK00XX-P001A
ME@
C183
EMC@
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
470P_0402_50V7K
1
2 C181
@
1
2 C184
@
470P_0402_50V7K
A_HP_OUTR_R
2 0_0402_5%
@
D26
EMC_NS@
2
2
AZ5425-01F_DFN1006P2E2
1
1
2
D25
EMC_NS@
EMC_NS@
D24
2
AZ5425-01F_DFN1006P2E2
1
1
2
2
AZ5425-01F_DFN1006P2E2
1
1
D2
EMC_NS@
2
2
AZ5425-01F_DFN1006P2E2
1
2
D1
EMC_NS@
2
2
1
1
7
AZ5425-01F_DFN1006P2E2
For EMI
2
1
2
G1
G2
JHP1
A_HP_OUTL_R
2 0_0402_5%
PLUG_IN
EMC_NS@
56P 50V J NPO 0402
CA26
2
1
Audio Jack
RING3_CONN
RING2_CONN
A_HP_OUTL_R
A_HP_OUTR_R
PLUG_IN
C185
1
EMC_NS@
33P_0402_50V8J
CA25
2
EMC_NS@
CA24
2
1
1
2
3
4
CD@ CD@
RING3_CONN
HP_OUTL
R190 1
33P_0402_50V8J
1
EMC_NS@
CA23
2
22P_0402_50V8-J
1
EMC_NS@
CA22
22P_0402_50V8-J
68P_0402_50V8J
2
EMC@
A
1
1
2
Close to Pin11,13,16
HDA_RST_AUDIO#
HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO
RA27 1 EMC_NS@
2 HDA_BITCLK_AUDIO
HDA_SDIN0
27_0402_5%
SPK_L+_CONN
SPK_L-_CONN
2 BLM18PG221SN1D_2P
2 BLM18PG221SN1D_2P
470P_0402_50V7K
GNDA
Use 250mils wide trace bridging
AGND and DGND at codec
For EMI
RA30 1
RA34 1
100P_0402_50V8J
2
SPK_L+
SPK_L-
100P_0402_50V8J
2
CA39
CA38
1
1
GND
EMC_NS@
1
1
100P_0402_50V8J
2
2
EMC_NS@
2
2
100P_0402_50V8J
1
CA19
.1U_0402_10V6-K
CA18
.1U_0402_10V6-K
CA16
4.7U_0603_10V6-K
CA15
4.7U_0603_10V6-K
1
RA32
RA33
470P_0402_50V7K
CA32
DMIC_DATA
B
2
2
EMC@
EMC@
220P_0402_50V7K
CA30
DMIC_CLK
CD@ +5VD
15_0402_5% 1 CD@
15_0402_5% 1 CD@
220P_0402_50V7K
CA29
CD@
JSPK1
JSENSE
on
PLUG_IN
Codec_CX11802
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Wednesday, May 13, 2015
Date:
Rev
0.2
CG510
3
2
Sheet
1
43
of
59
5
4
3
For EMI
+3VL
2
D
2 0_0402_5%
2
1
CE7
2
1
+3VALW _R
CE8
2
1
2
CE9
@
1
CE10
2
1
1
CE11
RE54 1
2
@
2
2 0_0603_5%
1
CE4
.1U_0402_10V6-K
EC_AGND 2
CE5
1000P_0402_50V7K
RE5
10K_0402_5%
@
EC_AGND
LAN_W AKE#
45
KSI[0..7]
KSI[0..7]
45
C
KSO[0..17]
KSO[0..17]
+3VALW _R
RPE2
2
1
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK1
EC_SMB_DA1
3
4
PAD
PAD
PAD
PAD
PAD
2.2K_0404_4P2R_5%
+3VS
KSI7
KSI6
W RST#
RPE3
1
2
PAD
PAD
PAD
EC_SMB_CK2
EC_SMB_DA2
4
3
1
1
1
1
1
1
1
1
@
IT1
@
IT2
@
IT3
@
IT4
@
IT5
@
IT6
@
IT7
@
IT8
For factory EC flash
2.2K_0404_4P2R_5%
EC_ON RE58 2
5
@
RE24 1
H_PECI
45
1 0_0402_5%
ON/OFF
52,53
52,53
2 43_0402_5%
EC_SMB_CK1
EC_SMB_DA1
7,19
7,19
EC_SMB_CK2
EC_SMB_DA2
+3VL
EC_SMB_CK1
EC_SMB_DA1
PECI_EC
EC_SMB_CK2
EC_SMB_DA2
41
8
RE35 1
@
2 10K_0402_5% ON/OFF
RE36 1
@
2 10K_0402_5% BKOFF#
RE38 1
2 10K_0402_5% LID_SW #
RE40 1
2 10K_0402_5% BKOFF#
@
2 0_0402_5%
USB_ON#
USB_ON#
58
59
60
61
62
63
64
65
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
56
57
112
125
VSTBY0
GPE4
74
PS2CLK0/TMB0/CEC/GPF0
PS2DAT0/TMB1/GPF1
GPF2
PS2
GPF3
PS2CLK2/GPF4
PS2DAT2/GPF5
EXTERNAL SERIAL FLASH
GPH3/ID3
GPH4/ID4
GPH5/ID5
GPH6/ID6
NC1
NC2
NC3
NC4
SPI Flash ROM
UART
AC_IN#
LID_SW#
EGAD/GPE1
EGCS#/GPE2
EGCLK/GPE3
Bus
GPIO
GPJ1
SSCE0#/GPG2
SSCE1#/GPG0
DSR0#/GPG6
DTR1#/SBUSY/GPG1/ID7
CRX0/GPC0
CTX0/TMA0/GPB2
RI1#/GPD0
RI2#/GPD1
TACH2/GPJ0
TACH1A/TMA1/GPD7
TACH0A/GPD6
L80HLAT/BAO/GPE0
L80LLAT/GPE7
WAKE UP
GINT/CTS0#/GPD5
RTS1#/GPE5
CLKRUN#/GPH0/ID0
CK32KE/GPJ7
CK32K/GPJ6
DAC2/TACH0B/GPJ2
DAC3/TACH1B/GPJ3
DAC4/DCD0#/GPJ4
DAC5/RIG0#/GPJ5
GPIO
78
79
80
81
85
86
87
88
89
90
SUSP#
MAINPW ON
RE65
100K_0402_5%
TP_CLK
RE12 2
1 4.7K_0402_5%
TP_DATA
RE13 2
1 4.7K_0402_5%
+5VALW
{54}
USB_ON#
RE15 1
IT8586E-AX_LQFP128_14X14
+3VALW _R
PCH_PW R_EN
ACOFF
PCH_PW ROK
46
53
8,10
EC_SPI_CS0#
EC_SPI_SI
EC_SPI_SO
EC_SPI_CLK
ACIN#
LID_SW #
LID_SW #
82
83
84
45
VDDQ_PGOOD
GPG2
EC_ADAPTER_R
SYSON
BKOFF#
RE18 1
SUSP#
RE19 1
2 100K_0402_5%
SYSON
RE21 1
2 100K_0402_5%
SUS_VCCP
RE23 1
EC_ADAPTER_R
RE28 1
55
33
PM_SLP_S3#
PM_SLP_S4#
NOVO#
RE25 2
@
1 0_0402_5%
RE29 1
@
2 0_0402_5%
PM_SLP_S5#
ME_FLASH
1 10K_0402_5%
@
1 0_0402_5%
2 100K_0402_5%
@
2 100K_0402_5%
PCIE_W AKE#
8
8
8
8
EC_FAN_SPEED
39
RE30 1
@
PM_SLP_S3#
CE21 1
SYSON
CE13 1
2
1000P_0402_50V7K
EMC_NS@
2
1000P_0402_50V7K
B
EMC_NS@
2 0_0402_5% VGA_AC_DET
VGA_AC_DET
19
EMC Request
59
RE34
VR_HOT#
1
@
2 0_0402_5%
H_PROCHOT#
5
RTC_RST#
H_PROCHOT#_EC
QE1
D
2
1
G
3
S
2
CE14
47P_0402_50V8J
@
QE3
EC_RTCRST#_ON
7
D
2
G
+3VL
1
@
RE45 2
2 100K_0402_5%
7
45
1
2 47P_0402_50V8J
1
2 100P_0402_50V8J
ACIN#
@ CE17
1
2 100P_0402_50V8J
ON/OFF
@ CE18
1
2 1U_0402_6.3V6K
RE42
10K_0402_5%
+3VS
1
2
1
S 2N7002KW _SOT323-3
RE50
100K_0402_5%
2
@ CE15
BATT_TEMP @ CE16
ACIN#
D
QE2
2
CE19
.1U_0402_10V6-K
ACIN
G
A
53
SPI_CS0#
SPI_CS0#
RE47 2
@
1 0_0402_5%
SPI_SI
EC_SPI_SO
RE48 2
@
1 0_0402_5%
SPI_SO
EC_SPI_CLK
RE49 2
@
1 0_0402_5%
SPI_CLK
SPI_SI
7
SPI_SO
7
2
SPI_CLK
7
1
@2
.01U_0402_16V7-K
EC_SPI_SI
7NOVO#
S
3
RE46 2
when mirror, GPG2 pull high
when no mirror, GPG2 pull low
EC_SPI_CS0#
C48
GPG2
1 10K_0402_5%
1 10K_0402_5%
@
43
SYSON
BKOFF#
EC_FAN_SPEED
SUSP#
55
EC_MUTE#
1
+3VALW _R
RE44 2
2 100K_0402_5%
45
45
Clock
PECI_EC
GPG2
RE51
0_0402_5%
Reserve for VGA_AC_DET
+3VL
@
2 100K_0402_5%
C
EC_ON
for EC version update to EX, manual modify PN to FX
RE43 2
2 10K_0402_5%
8
TP_CLK
TP_DATA
2N7002KW _SOT323-3
GPG2
2 10K_0402_5%
RE52
0_0402_5%
@
EC_AGND
A
@
@
+3VALW _R
1 0_0402_5%
PBTN_OUT#
TP_CLK
TP_DATA
108
109
77
100
106
104
107
119
123
18
21
76
48
47
19
20
1
33
RE57 2
96
97
98
99
101
102
103
105
1
RE9
+5VS +3VS
54
ENBKL
EC_ON_GPIO
RE7
ENBKL
46,55,56,57
EC_RTCRST#_ON
H_PROCHOT#_EC
RE11 1
LPC_FRAME#
57
NTC_V1
39
NTC_V2
39
BATT_TEMP
52
VR_IMVP_IMON
59
VR_CPU_PW ROK
10,59
ADP_I
53
BATT_TEMP
EC_FAN_PW M
2
SUS_VCCP
LAN_W AKE#
SUSP#
45
45
{11}
8
39
2
66
67
68
69
70
71
72
73
EC_FAN_PW M
45
10K_0402_5%
1
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)
AVCC
26
50
92
114
121
127
12
DAC
PWRSW#
SM
XLP_OUT
SMCLK1/GPC1
SMDAT1/GPC2
SMCLK2/PECI/GPF6
SMDAT2/PECIRQT#/GPF7
CRX1/SIN1/SMCLK3/GPH1/ID1
CTX1/SOUT1/GPH2/SMDAT3/ID2
2
128
EC_LID_OUT#
AC_PRESENT
11
KSI0/STB#
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
KSI5
KSI6
KSI7
KSO0/PD0
Int. K/B
KSO1/PD1
Matrix
KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15
KSO16/SMOSI/GPC3
KSO17/SMISO/GPC5
33
35
93
EC_RSMRST#
ADC
VSS1
9
8
+3VL
1
EC_VR_ON
ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC3/GPI3
ADC4/GPI4
ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
IT8586E/AX
LQFP-128L
110
111
115
116
117
118
94
95
ON/OFF
RE27
59
B
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
LPC
PW R_LED#
BATT_CHG_LED#
BATT_LOW _LED#
VCCST_PW RGD
SYS_PW ROK
EC_FAN_PW M
BEEP#
43
SUS_VCCP
VCCST_PW RGD
2
1
EC_RX
EC_TX
PLT_RST#
PWM
24
25
28
29
30
31
32
34
120
124
RE10 1
3
EC_SMI#
EC_RX
EC_TX
PLT_RST#
EC_SCI#
PCH_CMOSP
PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
PWM6/SSCK/GPA6
PWM7/RIG1#/GPA7
TMRI0/GPC4
TMRI1/GPC6
1
9
40
40
CE12
8,19,32,37,40
1U_0402_6.3V6K
9
2
46
1
37
2
2 100K_0402_5%
CLK_PCI_EC
W RST#
KBRST#/GPB6
SERIRQ/GPM6
LFRAME#/GPM5
LAD3/GPM3
LAD2/GPM2
LAD1/GPM1
LAD0/GPM0
LPCCLK/GPM4
WRST#
ECSMI#/GPD4
PWUREQ#/BBO/SMCLK2ALT/GPC7
LPCPD#/GPE6
LPCRST#/GPD2
ECSCI#/GPD3
GA20/GPB5
1
1
4
5
6
7
8
9
10
13
14
15
16
17
22
23
126
LPC_FRAME#
AVSS
@
RB751V-40_SOD323-2
RE8
KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
7,32
7,32
7,32
7,32
7,32
8
1
2
27
49
91
113
122
DE1
1
LAN_W AKE#
+3VS
EC_FAN_SPEED
75
9
9,32
+3VALW _R
D
minimum trace width 12 mil
VSS2
VSS3
VSS4
VSS5
VSS6
W RST#
VCC
VBAT
19
VCORE
UE1
3
CD@
Change RE6 to 0ohm jump
1
CE6
2 0_0603_5%
1
@
1
@
2
+3VALW _EC
RE53 1
All capacitors close to EC
+3VALW _R
+3VS
1
+3VALW _EC
+3VALW _R
VCOREVCC
.1U_0402_10V6-K
RE6
+3VALW
+3VALW _R
CE3
1
2
2 0_0603_5%
@
.1U_0402_10V6-K
CE2
10P_0402_50V8J
EMC_NS@
1
.1U_0402_10V6-K
CE1
220P_0402_50V7K
EMC@
RE3
Close EC
1
2
1
2 10_0402_5%
@
.1U_0402_10V6-K
1
2
.1U_0402_10V6-K
RE2
1
.1U_0402_10V6-K
CLK_PCI_EC
2 0_0603_5%
.1U_0402_10V6-K
For ESD
PLT_RST#
1
RE1
RE66 1
@
2 0_0402_5%
Title
LC Future Center Secret Data
Security Classification
Issued Date
2N7002KW _SOT323-3
2015/02/27
Deciphered Date
EC ITE8586LQFP
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
44
of
59
5
4
ON/OFF switch
+3VL
3
1
2
KSI[0..7]
SW5
1
1
R83
100K_0402_5%
@
KSI[0..7]
D15
KSO[0..17]
2
R85
1
2 0_0402_5%
@
3
ON/OFF
3
JKB1
44
KSO[0..17]
EVQP7L01K SPST
NOVO_BTN#
1
44
BAT54CW_SOT323-3
D
2
+3VL
2
+3VALW
R111
100K_0402_5%
@
R114
100K_0402_5%
ON/OFF
44
1
ON/OFF
2
2 0_0402_5%
@
1
ON/OFFBTN#
1
R119 1
ON/OFFBTN#
SW6
NOVO_BTN#
ON/OFFBTN#
4
1
1
2
1
1
2
AZ5215-01F_DFN1006P2E2
2
TP_CLK
TP_DATA
TP/B Connector
2
R160 1
@
0_0402_5%
Hall Sensor
JTP1
1
2
3
4
5
6
GND1
GND2
7
8
ACES_50503-0060N-001
ME@
EMC_NS@
1
U14
C1104
0.01U_0402_25V7K
D16
1
PWR_LED#
1
2
1
1
2
EMC_NS@
TP_P6
OUTPUT
2
+VCC_LID
2
C1105
.1U_0402_10V6-K
VCC
LID_SW#
3
D17
LID_SW#
44
EMC_NS@
For EMC
DT5
2
1
1
B
2
EVQPLHA15_4P
R262
1
2
@
0_0402_5%
2
GND
AH9247NTR-G1_SOT23-3
2
2
5
EVQPLHA15_4P
1
A
A1
GND1
GND2
B
B1
4
3
6
5
2
1
A
GND1
A1
B1
+3VL
1
EMC_NS@
For 15"
R142 1
2 1.5K_0402_5%
+5VALW
R143 1
2 470_0402_5%
+3VALW
LTW-C193TS5
1
AZ5425-01F_DFN1006P2E2
LED1
B
5
For 14"
PWR_LED#
GND2
1
1
2
5
GND1
GND2
B1
2
15@
EMC_NS@
6
14@
4
GND
3
TP-R
6
1
5
TP-R
DT4
1
TP-L
6
SW4
2
5
DT3
TP_RIGHT Button
TP_P6
2
TP-L
GND1
4
3
GND
15@
EMC_NS@
AZ5215-01F_DFN1006P2E2
4
AZ5215-01F_DFN1006P2E2
SW3
GND2
DAT
EVQPLHA15_4P
3
6
DAT
B
A1
3
SW2
DT2
TP_RIGHT Button
B1
CLK
4
2
2
CLK
4
2
1
VDD
3
14@
1
EVQPLHA15_4P
2
For 15"
6
SW1
A1
TP_P6_CON
AZ5215-01F_DFN1006P2E2
1
TP_P5_CON
1
1
TP_P5
1
TP_LEFT Button
TP_P5
2
TP_LEFT Button
TP_P4_CON
2
TP_P6_CON
VDD
44
AZC199-02S.R7G_SOT23-3
For EMC
TP_P5_CON
1
LED
C
DT1
1
C116
100P_0402_50V8J
100P_0402_50V8J
C115
2
AZ5215-01F_DFN1006P2E2
For 14"
TP_P4_CON
@1
A
TP_P6
2
B
TP_P5
@1
2
A
TP_P6
2
R271 1
0_0402_5%
2
R272 1
0_0402_5%
2
R273 1
0_0402_5%
2
R274 1
@
0_0402_5%
2
R275 1
@
0_0402_5%
2
R276 1
@
0_0402_5%
1
1
2
3
4
5
6
TP_CLK
TP_DATA
TP_P4_CON
TP_P5_CON
TP_P6_CON
TP_CLK
TP_DATA
B
TP_P5
44
44
C114
.1U_0402_10V6-K
2
R141 1
0_0402_5%
D
For EMC
AZ5215-01F_DFN1006P2E2
+3VS
TP_PWR
27
28
ACES_88514-02601-071
ME@
3
C
EMC@
GND1
GND2
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2
+5VS
D21
2
EMC@
AZ5215-01F_DFN1006P2E2
3
EVQP7L01K SPST
D20
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
4
NOVO#
15"
K/B Connector
2
2
NOVO_BTN#
NOVO#
1
+3VALW
R82
100K_0402_5%
44
2
2
2
EMC_NS@
BATT_LOW_LED#
BATT_LOW_LED#
D18
LED2
1
2
LTST-C193KFKT-LC
1
AZ5425-01F_DFN1006P2E2
1
44
EMC_NS@
A
2
2
A
BATT_CHG_LED#
BATT_CHG_LED#
LED3
1
2
R144 1
2 1.5K_0402_5%
+5VALW
1
AZ5425-01F_DFN1006P2E2
1
LTW-C193TS5
D19
Title
LC Future Center Secret Data
Security Classification
EMC_NS@
Issued Date
Deciphered Date
2013/08/05
KBD/PWR/IO/LED/TP Conn.
2
2015/02/27
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2
44
Size Document Number
Custom
Date:
5
4
3
2
1
Rev
0.2
CG510
Wednesday, May 13, 2015
Sheet
45
of
59
A
B
C
D
Load Switch
+5VALW To +5VS
+3VALW To +3VS
R1871
1
2 0_0402_5%
+3VS, C173 --> 2.74ms
+5VS, C176 --> 2.03ms
+5VALW
R27 1
2 0_0402_5%
C177
1U_0402_6.3V6K
1
C180
1U_0402_6.3V6K
@
+3VALW
1
2
2
C179
1U_0402_6.3V6K
@
3
5VSON
1
5VSON
4
+5VALW
2
5
3VSON
6
7
1
2
VIN1_1
VIN1_2
VOUT1_2
VOUT1_1
EN1
SS1
BIAS
GND
EN2
SS2
VIN2_1
VIN2_2
VOUT2_2
VOUT2_1
GPAD
C178
1U_0402_6.3V6K
@
1
+5VS
U13
1
2
SUSP#
Need Short
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
3VSON
E
14
13
J12
+5VS_LS
12
1
C176 1
2 1000P_0402_50V7K
C173 1
2 2200P_0402_25V7-K
1
@
2
2
JUMP_43X118
1
11
10
2
+3VS_LS
9
8
1
J11
@
1
2
C174 @
0.1U_0402_10V7-K
+3VS
2
JUMP_43X118
1
15
Need Short
APL3523AQBI-TRG_TDFN14_2X3
2
C175 @
0.1U_0402_10V7-K
+5VALW
+3VALW
+3VALW_PCH
+5VLP
2
R155
100K_0402_5%
@
1
2
1
34
2
2
2
1
2
C130
0.01U_0402_25V7K
@
Q6A
44,55,56,57
6
1
C129
.1U_0402_10V6-K
@
S 2N7002KW_SOT323-3
R159
47_0603_5%
@
SUSP
SUSP
D
Q6B
D
2
SUSP#
5
G
SUSP
G
PCH_PWR_EN#_R
R162
100K_0402_5%
@
2
2N7002KDWH_SOT363-6
44
PCH_CMOSP
R163 1
2
0_0402_5%
@
1
2
S
S 2N7002KDWH_SOT363-6
4
1
G
@
3
D
2
G
PCH_PWR_EN
Q29
Id=3.2A
D
44
LP2301ALT1G_SOT23-3
S
Q30
PCH_PWR_EN
+0.675VS
R161
100K_0402_5%
PCH_PWR_EN#
1
2 100K_0402_5%
1
2
@
1
R158 1
3
PCH_PWR_EN#_R
2
1
1
R278
0_0603_5%
3
1
2
C131
.1U_0402_10V6-K
@
2
R87
100K_0402_5%
@
3
3
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, May 14, 2015
Date:
Rev
0.2
CG510
C
D
Sheet
E
46
of
59
3
PU904
B5
3
+3VALW
1
DPWROK_EC
B1
4
PCH_RSMRST#
EC
5
EC_ON
A3
B4
PBTN_OUT#
V
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_SUS#
12
CPU_PLTRST#
SYS_PWROK
V
ON/OFF
PCH
6
PCH_PWROK
13
14
PM_DRAM_PWRGD
H_CPUPWRGD
C
B3
+3V_PCH
V
V
BATT
A4
B+
D
Q25,+3V_PCH
15
16
CPU
V V
BATT
MODE
A2
2
V
PU301
V
V V
VIN
PCH_PWR_EN#
1
V V
A1
V
AC
MODE
A2
+3VLP
V V V
B2
D
2
V
4
V
5
C
V
NOVO
NVDD_PWR_EN
(DIS)
+1.35V
PU501
+VGA_CORE
PU801
V
7
V
SYSON
VR_REDY
V
Vb
11
DGPU_PWROK
V
8
+3VS_VGA
Q27
V
V
PU602
+1.5VS
B
VGA
PU502
+0.675V
PU701
+1.05VS
V
SUS_VCCP
+1.05VSP_VGA
PU702
Q32
+3VS
V
9
V
SUSP#,SUSP
+1.5VS_VGA
PU601
V
V
B
Q31
+5VS
V
V
V
VR_ON
V
Va (DIS)
10
PU901
+CPU_CORE
V
DGPU_PWR_EN
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
2013/08/05
Deciphered Date
Power sequence Block
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
3
2
Sheet
1
47
of
59
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Virtual symbol
2013/08/05
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
Custom
Date:
2
Rev
0.1
CG510
Friday, May 15, 2015
Sheet
1
48
of
59
5
4
3
2
1
1
1
1
1
NH7
HOLEA
H8
HOLEA
PAD_C6P5D2P3
PAD_O2P8X3P3D2P8X3P3N
PAD_C6P5D2P3
D
H9
HOLEA
H11
HOLEA
H13
HOLEA
PAD_C6P5D2P3
1
PAD_C6P5D2P3
FD6
1
PAD_C6P5D2P3
FD5
1
PAD_C6P5D2P3
FD4
1
PAD_C6P5D2P3
FD3
1
H6
HOLEA
1
H5
HOLEA
1
H4
HOLEA
1
H3
HOLEA
1
PAD_C6P5D2P3
H2
HOLEA
1
1
H1
HOLEA
FD2
1
D
FD1
1
PCB Fedical Mark PAD
PAD_CB6P0D3P7
PAD_CB6P0D3P7
CPU
C
C
GP4
PAD_RT2P65X2P2
@
1
1
1
PAD_CT5P0B6P0D3P2
Stand Off
1
1
pad_ct6p5b5p5d2p3
PAD_CT5P0B6P0D3P2
1
GP3
PAD_RT2P65X2P2
@
1
GP2
PAD_RT2P65X2P2
@
1
GP1
PAD_RT2P65X2P2
@
1
H15
HOLEA
1
NH14
HOLEA
1
H12
HOLEA
1
H10
HOLEA
pad_c2p8d2p8n
CHASSIS1_GND
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
Hole
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
5
4
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
Sheet
1
49
of
59
5
4
B+
Silergy
SY8208CQNC
Converter
FOR SYSTEM
D
Adaptor
EC_ON
3
EN
Silergy
SY8868QMC
QFN10_2X2
Switch Mode
+5VALW/5A
PGOOD
ALW_PWRGD
SYSON
S5
SUSP#
S3
PGOOD
B
PGOOD
ALW_PWRGD
+1.5VSP/1A
FOR VDDR
TI
TPS51716RUKR
WQFN20_3X3
Switch Mode
FOR DDR
EN
PGOOD
+1.35V/12A
Silergy
SY8032ABC
SOT23-6
Switch Mode
+0.675VS/2A
PGOOD
C
+1.05VSP_VGA/2A
FOR VDDR
EN
PAGE 46
SMBus
EN
ANPEC
APL5930KAI-TRG_SO8
LDO
+3VALW/4A
SUSP#
TI
BQ24737RGRR
Battery Charger
Switch Mode
+1.05VS/5A
+3VLP/ 100mA
PAGE 39
C
D
FOR VDDR
SUSP#
Silergy
SY8206BQNC
Converter
FOR SYSTEM
EN
1
+5VLP/ 100mA
PAGE 39
EC_ON
2
VR_ON
EN
Onsemi
NCP81101MNTXG
QFN28_4X4
Switch Mode
FOR CPU Core PGOOD
Battery
Li-ion
4S1P/41WH
VIDs
NVDD_PWR_EN
EN
PGOOD_NB
Onsemi
NCP81172MNTWG
QFN24_4X4
Switch Mode
FOR GPU VDDC
PGOOD
PGOOD
CPU Core/14A/32A
VGATE
B
+VGA_CORE/31A
VGA_PWRGD
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
20140213
Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OFSize
R&D Document Number
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
3
2
1
Sheet
50
of
59
5
4
3
2
1
@
PJ101
2
1
VIN
PR9408 maybe adjust value
+3VL
EMC@
EMC@
0_0603_5%
2
0_0603_5%
2
VCCRTC
PD707
3
1
RTC_VCC
2
For EMI request
PC103
2
1
PL708 EMC_NS@
HCB2012KF-121T50_0805
1
2
PR9471
1
@
PR9408
1
PC104
1000P_0402_50V7K
@
470P_0402_50V7K
SINGA_2DC3161-000111F
ME@
PC102
2
1
D
2
1
APDIN
PC101
1000P_0402_50V7K
1
2
3
4
5
1
470P_0402_50V7K
JDCIN1
1
2
3
4
5
2
JUMP_43X79
PL707 EMC_NS@
HCB2012KF-121T50_0805
1
2
1
JRTC1
1
2
G1
G2
@
1
2
3
4
BAT_D
1 PR9400 2
1K_0603_5%
change to 1K SD01310018J
2
D
2
BAT54CW_SOT323-3
1
PC2
1U_0402_10V6K
ACES_50273-0020N-001
ME@
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
20140213
Deciphered Date
DCIN / RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
3
2
Sheet
1
51
of
59
5
4
3
2
1
@
PJ202
2
2
1
1
VMB
BATT+
1
PL201
HCB2012KF-121T50_0805
1
2
EMC_NS@
PL202
HCB2012KF-121T50_0805
1
2
EMC_NS@
PC201
1000P_0402_50V7K
2
2
PR202
100_0402_1%
1
2
D
PR201
100_0402_1%
2
1
1
JUMP_43X79
JBATT2
ME@
SUYIN_125022HB008M200ZL
1
1 2
2
EC_SMCA
9
3
EC_SMDA
10 GND1 3 4
11 GND2 4 5
12 GND3 5 6
GND4 6 7
7 8
8
PC202
0.01U_0402_25V7K
D
EC_SMB_CK1
44,53
EC_SMB_DA1
44,53
PR203
1
1
+3VALW
PR204
2
10K_0402_5%
BATT_TEMP
A/D
44
PD306
@
2
2
1
1
BATT_TEMP_IN
2
100K_0402_1%
AZ5215-01F_DFN1006P2E2
EC_SMCA
EC_SMDA
2
C
3
C
Reverse PD305 For EMI request
1
PD305
AZC199-02S.R7G_SOT23-3
@
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
20140213
Deciphered Date
BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
2
Sheet
1
52
of
59
PR9469
100K_0402_5%
2
P2-2
PR314
PQ998
2ACOFF-1
4
PC1317
0.1U_0402_25V6
1
2
2
2
DISCHG_G-1
1
1SS355_SOD323-2
1
PC320
10U_0805_25V6K
2
1
2
1
16251_SN
2ACOFF-1
PD302
D
5PACIN_N
1
2
PACIN_P
G
ACIN
1SS355_SOD323-2
S
44
PC1319
1000P_0402_25V7-K
ICHP
PC324
0.1U_0603_25V7-M
@
PC313
0.1U_0603_25V7-M
D
2
PACIN
G
S
PQ308A
2N7002KDWH_SOT363-6
ICHN
D
PQ307B
2N7002KDWH_SOT363-6
1
PJ711
2
JUMPER
@
4
S
C
CHARGER_GND
1
47K_0402_1%
C
5
G
PACIN_G
2
D
3
1
2
PR327
10K_0402_1%
2
CHARGER_GND
PC315
4.7U_0603_10V6-K
6
1
1
IACP
PACIN
1
PC1316
1U_0603_25V6M
3
2
1
2
IACM
2
PR306
200K_0402_1%
1
3
9
PQ308B
2N7002KDWH_SOT363-6
PD301
2
IACP
ACAV
VDDP
2
2.2_0603_5%
PD303
RB751V-40_SOD323-2
2
1
2
47K_0402_1%
1
VDDA
15
PR312
VIN
PR305
10K_0402_1%
2
IACM
COMP
VCC
D
PR304
1
3
VDDP
IAC
17
2
SCL
BST_CHG 1
1
1
6
2
1
2
8
16
12
1
2
3
4
7
VAC
3
1
IAC
BST
SDA
4
2
PC321
680P_0402_50V7K
@
2
10
LDR
ICHM
1
8
7
6
5
1
737_SCL
ICHP
2
4
11
PC317
1
PC319
10U_0805_25V6K
2
1
4
5
ICHN
737_SDA
1 PR9467 2
0_0402_5%
1
2
PR9466
100_0402_5%
3
1
CHARGER_GND
1
2
0_0402_5%
PC1315
0.47U_0402_25V6K
VDDP
CHARGER_GND
PR309
1
ADP_I
PC318
100P_0402_50V8J
PR307
68K_0402_1%
PACIN
ACOFF
EC_SMB_CK1
ADP_I
1
3
P2_G1
6
2N7002KDWH_SOT363-6
S
44
44,52
44
IACM
IACP
2
PR313
10_0402_5% 2
PR9468
10_0402_5% 2
2
0.47U_0603_25V6-K
DL_CHG
1
1
ICHP
PU911
OZ8682LN_QFN16_3X3
13
14
HDR
LX
PR315
PQ305
LTC015EUBFS8TL_UMT3F-3
PQ307A D
@
1
4.7_0805_5%
PR317
4
DH_CHG
EC_SMB_DA1
@
AON7408L_DFN8-5
BASE
PC303
10U_0805_25V6K
@
PC307
2200P_0402_50V7K
2
2
2
PC302
10U_0805_25V6K
@
44,52
LX_CHG
B+
PQ303
AO4407AL_SO8
PR316
0.01_1206_1%
4.7UH_PCMB063T-4R7MS_5.5A_20%
1
2 CHG
PQ311
@
P2-1
BATT+
PL302
5
PC306
4.7U_0805_25V6-K
1
2
PR303
200K_0402_1%
2
2
G
1
For EMI request
1
2
3
5
EMC@
1
100P_0402_50V8J
3
PC305
4.7U_0805_25V6-K
1
2
2
1
1P2_G2
2
PC308
0.1U_0603_25V7-M
2
1
2
3
LTA044EUBFS8TL_UMT3F-3
4
2
1
PC301
1
2
PQ304
1
PR302
200K_0402_5%
1
PL710
HCB2012KF-121T50_0805
1
2
1
D
PQ309
AON7408L_DFN8-5
PR301
0.01_1206_1%
PC1318
0.1U_0402_25V6
1
2
4
VIN
1
2
3
4
8
7
6
5
2
B+
P3
PQ302
SI4483ADY-T1-GE3_SO8
1
8
2
7
3
6
5
PC109
0.1U_0603_25V7-M
1
2
P2
PQ301
AO4407AL_SO8
3
1
4
PR347
1M_0402_5%
5
S 2N7002KW_SOT323-3
2
G
VIN
1
0_0402_5%
2
PR349
1M_0402_5%
2 1
2
PD706
RB751V-40_SOD323-2
2
1
1
PR308
20_0603_5%
VCC
PC314
0.47U_0603_25V6-K
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
20140213
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
CHARGER
Size
Document Number
Custom
Date:
5
4
3
2
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
53
of
59
5
4
3
2
1
B+
+3VBS 1
+3VALW _EN
2
PTP1@
PAD
0_0402_5%
44
MAINPW ON
C
1
0_0402_5%
@
1
1
PR339
1M_0402_5%
2
2
@ PC1054
0.1U_0402_25V6
2
PR417
2
1
EC_ON_R
1 1
D
2
1K_0402_1%
@
C
+3VL
+3VLP
PJ304
2
2
1
1
JUMP_43X39
G
2
PC425
2.2U_0603_10V7K
@
3
S
2N7002KW _SOT323-3
2
PR341
2
1
1
1
PQ405
2
1000P_0402_25V7-K
PR429
330_0603_5%
@
PR427
100K_0402_5%
@
@
PC1106
1000P_0402_50V9-J
@
PC1057
39
4A
@
PC1052
22U_0805_6.3V6M
PR338
4.7_0805_5%
@
PC1051
22U_0805_6.3V6M
2
1
15
14
13
2
1
1
+3VALW_P
PR9470
EC_ON_R
2
12
+3V_VIN 11
PR337
EC_ON
0_0402_5%
1
16
PC1050
22U_0805_6.3V6M
2
1
+3VLP
100mA
2
NC3
17
PC1049
22U_0805_6.3V6M
2
1
NC1
EN2
LDO
2
1
JUMP_43X79
1
GND3
PG
2
19
18
2
GND2
PJ303
+3VALW _P
1 2
LX2
1
2
1
BS
3
IN1
4
LX3
GND1
+3VALW
PL303
1
2
2.2UH_PCMB063T-2R2MS_8A_20%
+3V_LX
20
PC1055
4.7U_0603_6.3V6K
1
9
10
1
D
PU200
SY8286BRAC_QFN20_3X3
21
NC2
+3V_PW RGD
GND4
LX
OUT
8
FF
7
IN2
IN5
6
EN1
+3V_LX
44
PC1048
2
0.1U_0603_25V7-M
5
2
+3V_VIN
PR335
1M_0402_5%
1
2
2
@
1
1.5A
1
JUMP_43X79
PC1047
10U_0805_25V6K
1
1
2
PC1046
0.1U_0402_25V6
D
IN3
PJ302
2
@
@
2
+3VALW
PR342
100K_0402_5%
1
2
PR348
1M_0402_5%
1
1
2
@ PC1069
0.1U_0402_25V6
10
16
VCC
15
1
2+5VALW _P
0_0402_5%
100mA
+5VLP
17
1
PC1062
1U_0603_25V6M
1
2
PC1091
22U_0805_6.3V6M
13
PC1090
22U_0805_6.3V6M
2
1
14
PR340
4.7_0805_5%
@
PC1080
22U_0805_6.3V6M
2
1
FF
3.3UH_PCMB063T-3R3MS_6.5A_20%
5A
PJ306
+5VALW _P
PC1063
22U_0805_6.3V6M
2
1
OUT
+5VALW
@
2
2
PR351
LDO
NC1
NC2
1
LX1
LX2
LX3
@
PL304
1
+5VLX
1 2
EN1
EN2
0_0402_5%
0.1U_0603_25V7-M
6
19
20
2
+5VALW _EN 12
+5V_VIN
11
2
0_0402_5%
GND1
GND2
GND3
GND4
+5V_PW RGD
PC1061
1
2
+5VBS
9
1
1
7
8
18
21
PG
BS
2
0_0402_5% @
PR344
1
2
2
1
1
JUMP_43X79
@
B
PC1107
1000P_0402_50V9-J
@
PC1070
4.7U_0603_6.3V6K
1
2
2
PR346
1
PU201
5
4 IN1
3 IN2
2 IN3
IN4
2
EC_ON_R
B
PC1059
10U_0805_25V6K
@
+5V_VIN
PC1060
10U_0805_25V6K
2
JUMP_43X79
1
2.5A
1
PC1058
0.1U_0402_25V6
1
1
2
2
PJ305
2
SY8286CRAC_QFN20_3X3
B+
1
PR343
+3V_PW RGD
PC1072
1
2
1000P_0402_25V7-K
1
PR350
2
1K_0402_1%
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
20140213
PWR_3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
54
of
59
A
MODE
2
1.35V_GND
14
PR504
0_0402_5%
7
VTTREF
11
1
+3VALW
OTW#
1
1
1
1
+1.35V
DIS ------10A
@
@
PJ504
2
+0.675VSP
1.35V_FB
2
JUMP_43X118
@
PC519
22U_0805_6.3V6M
2
1
PC518
22U_0805_6.3V6M
2
1
2
2
PR509
41.2K_0402_1%
PGND
VTTREF
Mode
PR512
1K_0402_1%
2
1
VTTS
5
8
2
1
1
+0.675VS
JUMP_43X79
1
VTT
AGND
1A
+0.675VSP
220P_0402_50V7K
2
1
2
1
PC510
1M_0402_5%
PR513
PC517
22U_0805_6.3V6M
2
1
1.35V_L
1
PJ503
1.35V_L
PC515
22U_0805_6.3V6M
2
1
6
2
JUMP_43X118
@
1
VDDQ
1
3V3
FB
2
1
EMC_NS@
2.2_0805_5%
PR508
13
1.35V_FB
2
2
PG
SW
EMC_NS@
PC512
1200P_0402_50V7-K
3
4
1
4.7_0402_5%
PR507 2
12
EN2
BST
1
PC502
0.1U_0402_10V7K
1
2
@
VDDQ_PGOOD
2
1
PR502
100K_0402_1%
DDR_3V3
EN1
1.35V_SN
1
2
44
+3VALW
15
PC509
2
1
1
2
0_0402_5%
1U_0402_6.3V6K
SYSON
0.1U_0402_10V7K
SUSP#
PC501 @
44,46,56,57
44
S5_1.35V
VIN
1
16
PR503
PC508
10U_0603_6.3V6-M
S3_1.35V
10
2
1
2
PC505
10U_0805_25V6K
0_0402_5%
2
@
0_0402_5%
2 PR511 1
9
PU501
1
2
PR501
1
0.1U_0603_25V7-M
PC506
0_0603_5%
BST_1.35V 1 PR506 2 2
1
0.68UH_PCMB063T-R68MN_16A_20%
PL501
LX_1.35V
1
2
1U_0402_6.3V6K
PC511
CPU_DRAMPG_CNTL
@
PJ502
2
NB685GQ-Z_QFN16_3X3
5
10U_0805_25V6K
JUMP_43X79
1
D
1.35V_B+
1
PC504
2
1
1
EMC@
PC503
2
1
2
C
2A
@
PJ501
2
0.1U_0402_25V6
B+
B
PR510
33K_0402_1%
2
1.35V_GND
1.35V_GND
2
2
1.35V_GND
1
PJ505
2
JUMPER
@
1.35V_GND
3
3
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
1.35VS/+0.675VS
Size
Document Number
Custom
Date:
C
Rev
0.2
CG510
Saturday, May 09, 2015
D
Sheet
55
of
60
A
B
C
D
+1.5VSP
+1.5VS
50mA
50mA
PU912
PR609
1
2EN_1_5VSP
2
0_0402_5%
2
1
1
1
SET
5
PR608
21.5K_0402_1%
SHDN
APL5325BI-TRG_SOT23-5
JUMP_43X39 @
1
GND
1
1
2
PC613
220P_0402_50V7K
PC614
1U_0603_25V6M
@
VFB=0.8V
1
SUSP#
4
1
44,46,55,57
1
PJ712
VOUT
2
@
2
VIN
2
JUMP_43X39
3
1
1
2
1
PC612
4.7U_0603_6.3V6K
2
2
PJ713
2
+3VALW
1
PC1320
.1U_0402_10V6-K
SA000067W00
PR610
24K_0402_1%
2
@
2
2
3
3
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
20140213
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
+1.35VS_VGA/+1.5VS
Size
Document Number
Custom
Date:
C
Rev
0.2
CG510
Saturday, May 09, 2015
D
Sheet
56
of
59
5
4
3
2
1
2
+3VS
9
@
1
1_05VS_FB
2
+1.05VS
1
1
D
1
2
PC706
22U_0805_6.3V6M
1
2
2
1
JUMP_43X79
PC705
22U_0805_6.3V6M
GND
SY8868QMC_QFN10_2X2
PC711
0.01U_0402_25V7K
2
1
10
7
3
1
PC709
.1U_0402_10V6-K
FB
PJ702
2
@
4.7_0805_5%
PR703
6
2
1
@
SS
1
0.68UH_PCMC063T-R68MN_15.5A_20%
PC704
22U_0805_6.3V6M
5
2
OUT
1_05VS_LX
2
PC703
22U_0805_6.3V6M
EN
PL701
2
1
2
PG
LX3
2
2
0_0402_5%
1
1
LX1
LX2
@
8
PR705
SUS_VCCP
VIN
5A
1_05VS_EN
PR994
44
1
4
@ PR704
1
2
0_0402_5%
2
SUSP#
2
44,46,55,56
1_05VS_PVIN
PU701
@
1SNB_1_05VS 1
@
PC701
22U_0805_6.3V6M
JUMP_43X79
@
1
1
1
2
2
PC1066
2
1
2
47K_0402_5%
+5VALW
D
0.1U_0402_25V6
PJ704
PC702
22U_0805_6.3V6M
1_05VS_PG1
PR701
10K_0402_5%
@
@
PC710
680P_0402_50V7K
@
PR706
2
1
75K_0402_1%
PR707
100K_0402_1%
2
2
1 PC712
22P_0402_50V8-J
VFB=0.6V
Vo=VFB*(1+PR706/PR705)
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
20140213
+1.05VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
57
of
59
5
4
3
2
1
D
D
+VGA_B+
+3VGS
PJ710
2
1
1
B+
2
100_0402_5%
+VGA_CORE
2
1
PC1298
10U_0805_25V6K
1
2
2
OPT@
@
4.7_0805_5%
PR9435
1
1
LGATE1
PVCC
OPT@
PHASE2
2
PC1293
330U_2.5V_M
OPT@
+
2
PC1297
330U_2.5V_M
OPT@
SF000007300
1
OPT@
2
PC1296
680P_0402_50V7K
@
PC1301
4.7U_0603_6.3V6K
1
PVCC_VGA
18
17
2OPT@
1
PR9418
2
0_0603_5%
+5VS
OPT@
+VGA_B+
16
BOOT2
DGPU_PWROK
PR9425
10K_0402_5%
2
1
OPT@
+3VGS
SS time down
2
1
PC1276
10U_0805_25V6K
4
1
PQ993
AON6372_DFN8-5
OPT@
BOOT2_VGA
UGATE2_VGA
2
1
RT8812AGQW_WQFN20_3X3
PC1275
10U_0805_25V6K
PU910
2
SS
RGND
UGATE2
LGATE2
15
TON
20
19
1
C
+
1
1
BOOT1
2
4
3
EN
PSI
VID
5
REFADJ
UGATE1
PHASE1
VREF
OPT@
B
2
1
PR9448
1
REFIN
14
2
PC1269
1000P_0402_50V7K
@
PR9420
0_0402_5%
VCCSENSE_VGA OPT@ 2
1 VCC_SEN
+VGA_CORE
REFADJ
GND
1
VSSSENSE_VGA
6
7
REFIN
PC1257
+VGA_B+
1
2 VREF_VGA8
2700P_0402_50V7-K @
0.1U_0603_25V7K OPT@
OPT@
PR9465
2 OPT@ OPT@ 1
2
9
PR9449
0.1U_0402_25V6
PC1314 1
330K_0402_5%
2
1
PR9457
0_0402_5%
2.2_0603_5%
VSS_SEN
1
10
OPT@ 2
11
OPT@
2
21
100_0402_5%
1
2K_0402_1% OPT@
1
1
PR9459
2
18K_0402_1% OPT@
PC1259
1
2
2
2
PR9458
1
20K_0402_1% OPT@
PC1256
PR9447
2
PR9438
13K_0402_1%
2
1
UGATE1_VGA
PHASE1_VGA
PSI_VGA
PR9461
2
20K_0402_1% OPT@
PR9464
0_0402_5%
1
OPT@ 2
4
EN_VGA
PR9460
1
BOOT1_VGA
LGATE1_VGA
@
2700P_0402_50V7-K OPT@
VREF_VGA
PL705
0.24UH_PCME063T-R24MS1R145_35A_20%
1
2
PC1273
0.1U_0402_25V6
PC1258
1
2
OPT@
OPT@
DGPU_PWROK
DGPU_PWROK
OPT@
PQ992
AON6764_DFN8-5
GPU_VID
PGOOD
21
VCCSENSE_VGA
VSNS
VCCSENSE_VGA
13
VSSSENSE_VGA
20
OPT@
12
20
reserve
VSSSENSE_VGA
1000P_0402_25V7-K
C
PSI_VGA
PSI_VGA
1
19
EMC_OPT@
3
2
1
PR9429
PC1300
0_0603_5%
0.22U_0603_16V7K
2
1BOOT1_2_VGA 1
2
OPT@
OPT@
PR9430
0_0402_5%
NVVDD PWM_VID
NVVDD PWM_VID
PC1261
10P_0402_50V8J
2
1
19
PC1255
0.1U_0402_25V6
5
PQ991
AON6372_DFN8-5
OPT@
4
5
21,22
JUMP_43X79
@
3
2
1
EN_VGA
5
EN_VGA
PC1303
.1U_0402_10V6-K
OPT@
B
PR9424
PC1278
0_0603_5%
0.22U_0603_16V7K
2
1OPT@ BOOT2_2_VGA 1
2
OPT@
3
2
1
2
PR9443
PR9444
1
2
100K_0402_5%
@
OPT@
10K_0402_1%
2
2
1
PD705
RB751V-40_SOD323-2
OPT@
2
NVVDD PWM_VID
1
1
PXS_PWREN
1
4,21
PC1295
10U_0805_25V6K
2
2
PR9442
10K_0402_5%
@
EMC_OPT@
OPT@
OPT@
PL706
0.24UH_PCME063T-R24MS1R145_35A_20%
1
2
OPT@
PQ994
AON6764_DFN8-5
+VGA_CORE
4
PR9453
4.7_0805_5%
1
@
1
+
+ PC1281
PC1280
330U_2.5V_M
330U_2.5V_M
OPT@
@
2
2
2
1
3
2
1
2
LGATE2_VGA
OPT@
1
5
PHASE2_VGA
PC1302
680P_0402_50V7K
@
Issued Date
2015/02/27
Deciphered Date
OPT@
PC1292
22U_0805_6.3V6M
PC1291
22U_0805_6.3V6M
2
1
@
PC1290
22U_0805_6.3V6M
2
1
1
1
2
2
@
A
OPT@
Title
LC Future Center Secret Data
Security Classification
OPT@
PC1289
22U_0805_6.3V6M
2
1
OPT@
PC1288
22U_0805_6.3V6M
2
A
PC1287
22U_0805_6.3V6M
1
Change PC1280 from reserve to mount
Change PC1281 from mount to reserve
2013/08/05
PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Saturday, May 09, 2015
Date:
Rev
0.2
CG510
5
4
3
2
1
Sheet
58
of
59
4
3
1
CPU_PH
PJ708
JUMP_43X79
@
D
3A
2
2
1
PR9335
1
2
1
PC1158
68P_0402_50V8J
1
2
D
B+
1 PR9337 2
165K_0402_1%
PC1159
330P_0402_50V7K
1
2
2
1
VR_IMVP_IMON
PH901
220K_0402_5%_TSM0B224J4702RE
2
1
470P_0402_50V7K
PC1157
2
1
2
PR9334
27.4K_0402_1%
44
2
CORE_GND
1
CORE_GND
PR9338
75K_0402_1%
5
GND
PC988
68U_25V_M
1
1
2
2
1
2
1
1
2
2
1
PC1170
22U_0805_6.3V6M
2
PC1089
22U_0805_6.3V6M
2
1
@
PC1148
22U_0805_6.3V6M
PC1088
22U_0805_6.3V6M
2
1
2
PC1073
22U_0805_6.3V6M
2
1
1
1
2
1
@
C
PC1116
22U_0805_6.3V6M
PC1160
22U_0805_6.3V6M
2
1
1
2
1
2
PC1139
22U_0805_6.3V6M
1
2
1
2
PC1177
22U_0805_6.3V6M
PC1180
22U_0805_6.3V6M
PC1173
22U_0805_6.3V6M
PC1174
22U_0805_6.3V6M
2
1
2
1
PC1163
22U_0805_6.3V6M
1
2
1
2
PC1165
22U_0805_6.3V6M
PC1178
22U_0805_6.3V6M
1
2
1
2
1
2
1
PR9339
59K_0402_1%
1
PC626 @
10U_0603_6.3V6M
2
2
2
2
2
54.9_0402_1%
2
0_0402_5%
2
130_0402_1%
1
PR60
75_0402_1%
PC622
.1U_0402_10V6-K
1
1
1
PR31
1
1
PR9342
CORE_GND
PC1162
22U_0805_6.3V6M
@
10,44
2
VR_CPU_PW ROK
PR9098
PC1149
22U_0805_6.3V6M
1
2
2
2
PR47 @
10K_0402_5%
PC1176
22U_0805_6.3V6M
CORE_GND
CPU_SVID_CLK
@
@
+3VS
CORE_GND
VR_HOT#
@
0.1U_0402_25V6
5
3
2
1
For EMI request
CPU_SVID_DAT
+1.05VS
@
@
TSENSE
B
CPU_B+
1
2
2
PC620
.1U_0402_10V6-K
@
2
CPU_SVID_ALERT#
10
@
PC1155
0.01U_0402_25V7K
1
44
5
PR9331
+1.05VS
10
AON6764_DFN8-5
PQ39
PC621
680P_0402_50V7K
1K_0402_1%
PR9265
499_0402_1%
10
4
PH902
100K_0402_1%_TSM0B104F4251RZ
CPU_VR_ON
CPU_LG
PU908
NCP81101MNTXG_QFN28_4X4
1
10
2
PR617
4.7_0805_5%
CPU_PH
CPU_HG_R
PC97
1 PR80
2 1
2
2_0603_5%
0.22U_0603_25V7K
1
CORE_GND
1
EC_VR_ON
1
0.22UH_SPS-06CZ-R22M-V1_23A_20%
PC242
CORE_GND
1U_0603_25V6M
2
44
PL9
CPU_PH
CORE_GND
PC1164
22U_0805_6.3V6M
2.2_0603_5%
560P_0402_50V7-K
1
PR9343 2
@
0_0402_5%
PR9146
2
1
0_0402_5%
CPU_CORE
32A
PC1167
22U_0805_6.3V6M
2
1
2
1
2
3
4
5
6
7
1
+5VS
1
PC1254 @
1
2
+
@2
2
PR9145
1
PC113
@
AON6372_DFN8-5
PQ40
PC1156
0.01U_0402_25V7K
2
TSENSE 1
CORE_GND
CPU_LG
14
13
12
11
10
9
8
@
4
3
2
1
1
29
VBOOT
TSENSE
LG
PGND
SW
HG
BST
PC98
1
PC1154
1000P_0402_50V7K
CPU_VCC_SENSE
ROSC
COMP
FB
DIFFOUT
VSN
VSP
VCC
2
0_0402_5%
C
10
2
CPU_CSREF
2
2
1
ILIM
IOUT
CSCOMP
CSSUM
CSREF
IMAX
PVCC
21
20
19
18
17
16
15
2
PR365
0_0603_5%
CPU_HG_R 2
1CPU_HG
PR9332
69.8K_0402_1%
1
2
ENABLE
VR_HOT#
SDIO
ALERT#
SCLK
VR_RDY
VRMP
22
23
24
25
26
27
28
2
1
CPU_VSS_SENSE
CORE_GND
+5VS
2.2_0603_5%
PR1
17.4K_0402_1%
PR9402
12
1
1 CSCOMP
2
1
PR2
4.02K_0402_1%
1
2
2
PR9330
1K_0402_1%
1
2
PC1172
2.2U_0603_6.3V6K
PR9341
1
2
PC99
10U_0805_25V6K
CORE_GND
PC1171
1000P_0402_50V7K
PC100
10U_0805_25V6K
PC1181
10P_0402_50V8J
1
2
PR9340
102K_0402_1%
PC1065
10U_0805_25V6K
PC1153
330P_0402_50V7K
1
2
CORE_GND
10U_0805_25V6K
PR3
49.9_0402_1%
1
2
CPU_B+
CPU_CSREF
PR9333
16.5K_0402_1%
CSCOMP
CSSUM
2 PR9401 1CPU_CORE
1
10_0402_1%
140K_0603_1%
1
+
PC708
220U_D2_2.5VY_R6M
2 3
B
@
PJ3
1
2
JUMPER
@
CORE_GND
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/27
Deciphered Date
20140213
PWR_CPU Core
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date:
3
2
Document Number
Rev
0.2
CG510
Saturday, May 09, 2015
1
Sheet
59
of
59